Lines Matching refs:adev
540 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
541 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
542 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
544 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) in gfx_v8_0_init_golden_registers() argument
546 switch (adev->asic_type) { in gfx_v8_0_init_golden_registers()
548 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
551 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
554 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
559 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
562 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
565 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
571 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
574 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
577 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
582 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
585 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
588 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
593 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
596 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
599 amdgpu_program_register_sequence(adev, in gfx_v8_0_init_golden_registers()
608 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) in gfx_v8_0_scratch_init() argument
612 adev->gfx.scratch.num_reg = 7; in gfx_v8_0_scratch_init()
613 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()
614 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { in gfx_v8_0_scratch_init()
615 adev->gfx.scratch.free[i] = true; in gfx_v8_0_scratch_init()
616 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; in gfx_v8_0_scratch_init()
622 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_test_ring() local
628 r = amdgpu_gfx_scratch_get(adev, &scratch); in gfx_v8_0_ring_test_ring()
638 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v8_0_ring_test_ring()
646 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_ring_test_ring()
652 if (i < adev->usec_timeout) { in gfx_v8_0_ring_test_ring()
660 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v8_0_ring_test_ring()
666 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_test_ib() local
674 r = amdgpu_gfx_scratch_get(adev, &scratch); in gfx_v8_0_ring_test_ib()
691 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL, in gfx_v8_0_ring_test_ib()
702 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_ring_test_ib()
708 if (i < adev->usec_timeout) { in gfx_v8_0_ring_test_ib()
719 amdgpu_ib_free(adev, &ib); in gfx_v8_0_ring_test_ib()
721 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v8_0_ring_test_ib()
725 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) in gfx_v8_0_init_microcode() argument
736 switch (adev->asic_type) { in gfx_v8_0_init_microcode()
757 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
760 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
763 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()
764 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
765 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
768 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
771 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
774 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v8_0_init_microcode()
775 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
776 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
779 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
782 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
785 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v8_0_init_microcode()
786 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
787 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
790 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
793 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
794 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_init_microcode()
795 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
796 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
799 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
802 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
805 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_init_microcode()
806 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()
807 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()
809 if ((adev->asic_type != CHIP_STONEY) && in gfx_v8_0_init_microcode()
810 (adev->asic_type != CHIP_TOPAZ)) { in gfx_v8_0_init_microcode()
812 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()
814 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
818 adev->gfx.mec2_fw->data; in gfx_v8_0_init_microcode()
819 adev->gfx.mec2_fw_version = in gfx_v8_0_init_microcode()
821 adev->gfx.mec2_feature_version = in gfx_v8_0_init_microcode()
825 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
829 if (adev->firmware.smu_load) { in gfx_v8_0_init_microcode()
830 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; in gfx_v8_0_init_microcode()
832 info->fw = adev->gfx.pfp_fw; in gfx_v8_0_init_microcode()
834 adev->firmware.fw_size += in gfx_v8_0_init_microcode()
837 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; in gfx_v8_0_init_microcode()
839 info->fw = adev->gfx.me_fw; in gfx_v8_0_init_microcode()
841 adev->firmware.fw_size += in gfx_v8_0_init_microcode()
844 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; in gfx_v8_0_init_microcode()
846 info->fw = adev->gfx.ce_fw; in gfx_v8_0_init_microcode()
848 adev->firmware.fw_size += in gfx_v8_0_init_microcode()
851 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; in gfx_v8_0_init_microcode()
853 info->fw = adev->gfx.rlc_fw; in gfx_v8_0_init_microcode()
855 adev->firmware.fw_size += in gfx_v8_0_init_microcode()
858 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; in gfx_v8_0_init_microcode()
860 info->fw = adev->gfx.mec_fw; in gfx_v8_0_init_microcode()
862 adev->firmware.fw_size += in gfx_v8_0_init_microcode()
865 if (adev->gfx.mec2_fw) { in gfx_v8_0_init_microcode()
866 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; in gfx_v8_0_init_microcode()
868 info->fw = adev->gfx.mec2_fw; in gfx_v8_0_init_microcode()
870 adev->firmware.fw_size += in gfx_v8_0_init_microcode()
878 dev_err(adev->dev, in gfx_v8_0_init_microcode()
881 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()
882 adev->gfx.pfp_fw = NULL; in gfx_v8_0_init_microcode()
883 release_firmware(adev->gfx.me_fw); in gfx_v8_0_init_microcode()
884 adev->gfx.me_fw = NULL; in gfx_v8_0_init_microcode()
885 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_init_microcode()
886 adev->gfx.ce_fw = NULL; in gfx_v8_0_init_microcode()
887 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_init_microcode()
888 adev->gfx.rlc_fw = NULL; in gfx_v8_0_init_microcode()
889 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_init_microcode()
890 adev->gfx.mec_fw = NULL; in gfx_v8_0_init_microcode()
891 release_firmware(adev->gfx.mec2_fw); in gfx_v8_0_init_microcode()
892 adev->gfx.mec2_fw = NULL; in gfx_v8_0_init_microcode()
897 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) in gfx_v8_0_mec_fini() argument
901 if (adev->gfx.mec.hpd_eop_obj) { in gfx_v8_0_mec_fini()
902 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); in gfx_v8_0_mec_fini()
904 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); in gfx_v8_0_mec_fini()
905 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_fini()
906 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_fini()
908 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_fini()
909 adev->gfx.mec.hpd_eop_obj = NULL; in gfx_v8_0_mec_fini()
915 static int gfx_v8_0_mec_init(struct amdgpu_device *adev) in gfx_v8_0_mec_init() argument
924 adev->gfx.mec.num_mec = 1; in gfx_v8_0_mec_init()
925 adev->gfx.mec.num_pipe = 1; in gfx_v8_0_mec_init()
926 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; in gfx_v8_0_mec_init()
928 if (adev->gfx.mec.hpd_eop_obj == NULL) { in gfx_v8_0_mec_init()
929 r = amdgpu_bo_create(adev, in gfx_v8_0_mec_init()
930 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, in gfx_v8_0_mec_init()
933 &adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
935 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); in gfx_v8_0_mec_init()
940 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); in gfx_v8_0_mec_init()
942 gfx_v8_0_mec_fini(adev); in gfx_v8_0_mec_init()
945 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, in gfx_v8_0_mec_init()
946 &adev->gfx.mec.hpd_eop_gpu_addr); in gfx_v8_0_mec_init()
948 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); in gfx_v8_0_mec_init()
949 gfx_v8_0_mec_fini(adev); in gfx_v8_0_mec_init()
952 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); in gfx_v8_0_mec_init()
954 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); in gfx_v8_0_mec_init()
955 gfx_v8_0_mec_fini(adev); in gfx_v8_0_mec_init()
959 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); in gfx_v8_0_mec_init()
961 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
962 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v8_0_mec_init()
967 static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) in gfx_v8_0_gpu_early_init() argument
974 switch (adev->asic_type) { in gfx_v8_0_gpu_early_init()
976 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
977 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
978 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
979 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
980 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
981 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
982 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
983 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
984 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
986 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
987 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
988 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
989 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
993 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
994 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()
995 adev->gfx.config.max_cu_per_sh = 16; in gfx_v8_0_gpu_early_init()
996 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
997 adev->gfx.config.max_backends_per_se = 4; in gfx_v8_0_gpu_early_init()
998 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v8_0_gpu_early_init()
999 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1000 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1001 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1003 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1004 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1005 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1006 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1010 adev->gfx.config.max_shader_engines = 4; in gfx_v8_0_gpu_early_init()
1011 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()
1012 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1013 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1014 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1015 adev->gfx.config.max_texture_channel_caches = 8; in gfx_v8_0_gpu_early_init()
1016 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1017 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1018 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1020 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1021 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1022 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1023 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1027 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1028 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1029 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1030 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1032 switch (adev->pdev->revision) { in gfx_v8_0_gpu_early_init()
1040 adev->gfx.config.max_cu_per_sh = 8; in gfx_v8_0_gpu_early_init()
1050 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1057 adev->gfx.config.max_cu_per_sh = 6; in gfx_v8_0_gpu_early_init()
1066 adev->gfx.config.max_cu_per_sh = 4; in gfx_v8_0_gpu_early_init()
1070 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1071 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1072 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1073 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1075 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1076 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1077 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1078 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1082 adev->gfx.config.max_shader_engines = 1; in gfx_v8_0_gpu_early_init()
1083 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()
1084 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1085 adev->gfx.config.max_backends_per_se = 1; in gfx_v8_0_gpu_early_init()
1087 switch (adev->pdev->revision) { in gfx_v8_0_gpu_early_init()
1094 adev->gfx.config.max_cu_per_sh = 3; in gfx_v8_0_gpu_early_init()
1100 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1104 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v8_0_gpu_early_init()
1105 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1106 adev->gfx.config.max_gs_threads = 16; in gfx_v8_0_gpu_early_init()
1107 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1109 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1110 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1111 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1112 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1116 adev->gfx.config.max_shader_engines = 2; in gfx_v8_0_gpu_early_init()
1117 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()
1118 adev->gfx.config.max_cu_per_sh = 2; in gfx_v8_0_gpu_early_init()
1119 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1120 adev->gfx.config.max_backends_per_se = 2; in gfx_v8_0_gpu_early_init()
1121 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v8_0_gpu_early_init()
1122 adev->gfx.config.max_gprs = 256; in gfx_v8_0_gpu_early_init()
1123 adev->gfx.config.max_gs_threads = 32; in gfx_v8_0_gpu_early_init()
1124 adev->gfx.config.max_hw_contexts = 8; in gfx_v8_0_gpu_early_init()
1126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v8_0_gpu_early_init()
1127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v8_0_gpu_early_init()
1128 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v8_0_gpu_early_init()
1129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v8_0_gpu_early_init()
1135 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v8_0_gpu_early_init()
1136 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v8_0_gpu_early_init()
1138 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
1139 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v8_0_gpu_early_init()
1140 if (adev->flags & AMD_IS_APU) { in gfx_v8_0_gpu_early_init()
1163 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v8_0_gpu_early_init()
1165 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v8_0_gpu_early_init()
1168 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v8_0_gpu_early_init()
1169 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v8_0_gpu_early_init()
1170 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v8_0_gpu_early_init()
1173 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v8_0_gpu_early_init()
1174 adev->gfx.config.num_gpus = 1; in gfx_v8_0_gpu_early_init()
1175 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v8_0_gpu_early_init()
1178 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_gpu_early_init()
1190 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v8_0_gpu_early_init()
1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_sw_init() local
1200 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); in gfx_v8_0_sw_init()
1205 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); in gfx_v8_0_sw_init()
1210 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); in gfx_v8_0_sw_init()
1214 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v8_0_sw_init()
1216 gfx_v8_0_scratch_init(adev); in gfx_v8_0_sw_init()
1218 r = gfx_v8_0_init_microcode(adev); in gfx_v8_0_sw_init()
1224 r = gfx_v8_0_mec_init(adev); in gfx_v8_0_sw_init()
1231 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v8_0_sw_init()
1232 ring = &adev->gfx.gfx_ring[i]; in gfx_v8_0_sw_init()
1236 if (adev->asic_type != CHIP_TOPAZ) { in gfx_v8_0_sw_init()
1241 r = amdgpu_ring_init(adev, ring, 1024 * 1024, in gfx_v8_0_sw_init()
1243 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, in gfx_v8_0_sw_init()
1250 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_sw_init()
1258 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_sw_init()
1268 r = amdgpu_ring_init(adev, ring, 1024 * 1024, in gfx_v8_0_sw_init()
1270 &adev->gfx.eop_irq, irq_type, in gfx_v8_0_sw_init()
1277 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, in gfx_v8_0_sw_init()
1280 NULL, &adev->gds.gds_gfx_bo); in gfx_v8_0_sw_init()
1284 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, in gfx_v8_0_sw_init()
1287 NULL, &adev->gds.gws_gfx_bo); in gfx_v8_0_sw_init()
1291 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, in gfx_v8_0_sw_init()
1294 NULL, &adev->gds.oa_gfx_bo); in gfx_v8_0_sw_init()
1298 adev->gfx.ce_ram_size = 0x8000; in gfx_v8_0_sw_init()
1300 gfx_v8_0_gpu_early_init(adev); in gfx_v8_0_sw_init()
1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_sw_fini() local
1310 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); in gfx_v8_0_sw_fini()
1311 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); in gfx_v8_0_sw_fini()
1312 amdgpu_bo_unref(&adev->gds.gds_gfx_bo); in gfx_v8_0_sw_fini()
1314 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_sw_fini()
1315 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v8_0_sw_fini()
1316 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()
1317 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v8_0_sw_fini()
1319 gfx_v8_0_mec_fini(adev); in gfx_v8_0_sw_fini()
1324 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) in gfx_v8_0_tiling_mode_table_init() argument
1330 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v8_0_tiling_mode_table_init()
1343 switch (adev->asic_type) { in gfx_v8_0_tiling_mode_table_init()
1511 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
1607 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
1801 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
1897 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2092 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2188 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2359 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2455 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2627 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2723 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v8_0_tiling_mode_table_init()
2740 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) in gfx_v8_0_select_se_sh() argument
2760 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev, in gfx_v8_0_get_rb_disabled() argument
2778 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, in gfx_v8_0_setup_rb() argument
2787 mutex_lock(&adev->grbm_idx_mutex); in gfx_v8_0_setup_rb()
2790 gfx_v8_0_select_se_sh(adev, i, j); in gfx_v8_0_setup_rb()
2791 data = gfx_v8_0_get_rb_disabled(adev, in gfx_v8_0_setup_rb()
2797 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v8_0_setup_rb()
2798 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v8_0_setup_rb()
2807 adev->gfx.config.backend_enable_mask = enabled_rbs; in gfx_v8_0_setup_rb()
2809 mutex_lock(&adev->grbm_idx_mutex); in gfx_v8_0_setup_rb()
2811 gfx_v8_0_select_se_sh(adev, i, 0xffffffff); in gfx_v8_0_setup_rb()
2841 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v8_0_setup_rb()
2842 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v8_0_setup_rb()
2856 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) in gfx_v8_0_init_compute_vmid() argument
2877 mutex_lock(&adev->srbm_mutex); in gfx_v8_0_init_compute_vmid()
2879 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_init_compute_vmid()
2886 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_init_compute_vmid()
2887 mutex_unlock(&adev->srbm_mutex); in gfx_v8_0_init_compute_vmid()
2890 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) in gfx_v8_0_gpu_init() argument
2899 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
2900 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
2901 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
2903 adev->gfx.config.gb_addr_config & 0x70); in gfx_v8_0_gpu_init()
2905 adev->gfx.config.gb_addr_config & 0x70); in gfx_v8_0_gpu_init()
2906 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
2907 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
2908 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in gfx_v8_0_gpu_init()
2910 gfx_v8_0_tiling_mode_table_init(adev); in gfx_v8_0_gpu_init()
2912 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines, in gfx_v8_0_gpu_init()
2913 adev->gfx.config.max_sh_per_se, in gfx_v8_0_gpu_init()
2914 adev->gfx.config.max_backends_per_se); in gfx_v8_0_gpu_init()
2918 mutex_lock(&adev->srbm_mutex); in gfx_v8_0_gpu_init()
2920 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_gpu_init()
2940 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_gpu_init()
2941 mutex_unlock(&adev->srbm_mutex); in gfx_v8_0_gpu_init()
2943 gfx_v8_0_init_compute_vmid(adev); in gfx_v8_0_gpu_init()
2945 mutex_lock(&adev->grbm_idx_mutex); in gfx_v8_0_gpu_init()
2950 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v8_0_gpu_init()
2953 (adev->gfx.config.sc_prim_fifo_size_frontend << in gfx_v8_0_gpu_init()
2955 (adev->gfx.config.sc_prim_fifo_size_backend << in gfx_v8_0_gpu_init()
2957 (adev->gfx.config.sc_hiz_tile_fifo_size << in gfx_v8_0_gpu_init()
2959 (adev->gfx.config.sc_earlyz_tile_fifo_size << in gfx_v8_0_gpu_init()
2961 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v8_0_gpu_init()
2965 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) in gfx_v8_0_wait_for_rlc_serdes() argument
2970 mutex_lock(&adev->grbm_idx_mutex); in gfx_v8_0_wait_for_rlc_serdes()
2971 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_wait_for_rlc_serdes()
2972 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_wait_for_rlc_serdes()
2973 gfx_v8_0_select_se_sh(adev, i, j); in gfx_v8_0_wait_for_rlc_serdes()
2974 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v8_0_wait_for_rlc_serdes()
2981 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v8_0_wait_for_rlc_serdes()
2982 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v8_0_wait_for_rlc_serdes()
2988 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v8_0_wait_for_rlc_serdes()
2995 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, in gfx_v8_0_enable_gui_idle_interrupt() argument
3014 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) in gfx_v8_0_rlc_stop() argument
3021 gfx_v8_0_enable_gui_idle_interrupt(adev, false); in gfx_v8_0_rlc_stop()
3023 gfx_v8_0_wait_for_rlc_serdes(adev); in gfx_v8_0_rlc_stop()
3026 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) in gfx_v8_0_rlc_reset() argument
3038 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) in gfx_v8_0_rlc_start() argument
3046 if (!(adev->flags & AMD_IS_APU)) in gfx_v8_0_rlc_start()
3047 gfx_v8_0_enable_gui_idle_interrupt(adev, true); in gfx_v8_0_rlc_start()
3052 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) in gfx_v8_0_rlc_load_microcode() argument
3058 if (!adev->gfx.rlc_fw) in gfx_v8_0_rlc_load_microcode()
3061 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v8_0_rlc_load_microcode()
3064 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v8_0_rlc_load_microcode()
3071 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v8_0_rlc_load_microcode()
3076 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) in gfx_v8_0_rlc_resume() argument
3080 gfx_v8_0_rlc_stop(adev); in gfx_v8_0_rlc_resume()
3088 gfx_v8_0_rlc_reset(adev); in gfx_v8_0_rlc_resume()
3090 if (!adev->firmware.smu_load) { in gfx_v8_0_rlc_resume()
3092 r = gfx_v8_0_rlc_load_microcode(adev); in gfx_v8_0_rlc_resume()
3096 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, in gfx_v8_0_rlc_resume()
3102 gfx_v8_0_rlc_start(adev); in gfx_v8_0_rlc_resume()
3107 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) in gfx_v8_0_cp_gfx_enable() argument
3120 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_cp_gfx_enable()
3121 adev->gfx.gfx_ring[i].ready = false; in gfx_v8_0_cp_gfx_enable()
3127 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) in gfx_v8_0_cp_gfx_load_microcode() argument
3135 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v8_0_cp_gfx_load_microcode()
3139 adev->gfx.pfp_fw->data; in gfx_v8_0_cp_gfx_load_microcode()
3141 adev->gfx.ce_fw->data; in gfx_v8_0_cp_gfx_load_microcode()
3143 adev->gfx.me_fw->data; in gfx_v8_0_cp_gfx_load_microcode()
3149 gfx_v8_0_cp_gfx_enable(adev, false); in gfx_v8_0_cp_gfx_load_microcode()
3153 (adev->gfx.pfp_fw->data + in gfx_v8_0_cp_gfx_load_microcode()
3159 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
3163 (adev->gfx.ce_fw->data + in gfx_v8_0_cp_gfx_load_microcode()
3169 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
3173 (adev->gfx.me_fw->data + in gfx_v8_0_cp_gfx_load_microcode()
3179 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v8_0_cp_gfx_load_microcode()
3184 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) in gfx_v8_0_get_csb_size() argument
3213 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) in gfx_v8_0_cp_gfx_start() argument
3215 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_start()
3221 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v8_0_cp_gfx_start()
3225 gfx_v8_0_cp_gfx_enable(adev, true); in gfx_v8_0_cp_gfx_start()
3227 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4); in gfx_v8_0_cp_gfx_start()
3257 switch (adev->asic_type) { in gfx_v8_0_cp_gfx_start()
3296 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) in gfx_v8_0_cp_gfx_resume() argument
3311 ring = &adev->gfx.gfx_ring[0]; in gfx_v8_0_cp_gfx_resume()
3328 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v8_0_cp_gfx_resume()
3340 if (adev->asic_type != CHIP_TOPAZ) { in gfx_v8_0_cp_gfx_resume()
3353 if (adev->asic_type == CHIP_TONGA) { in gfx_v8_0_cp_gfx_resume()
3366 gfx_v8_0_cp_gfx_start(adev); in gfx_v8_0_cp_gfx_resume()
3377 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) in gfx_v8_0_cp_compute_enable() argument
3385 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_cp_compute_enable()
3386 adev->gfx.compute_ring[i].ready = false; in gfx_v8_0_cp_compute_enable()
3391 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev) in gfx_v8_0_cp_compute_start() argument
3393 gfx_v8_0_cp_compute_enable(adev, true); in gfx_v8_0_cp_compute_start()
3398 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) in gfx_v8_0_cp_compute_load_microcode() argument
3404 if (!adev->gfx.mec_fw) in gfx_v8_0_cp_compute_load_microcode()
3407 gfx_v8_0_cp_compute_enable(adev, false); in gfx_v8_0_cp_compute_load_microcode()
3409 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v8_0_cp_compute_load_microcode()
3413 (adev->gfx.mec_fw->data + in gfx_v8_0_cp_compute_load_microcode()
3421 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v8_0_cp_compute_load_microcode()
3424 if (adev->gfx.mec2_fw) { in gfx_v8_0_cp_compute_load_microcode()
3427 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v8_0_cp_compute_load_microcode()
3431 (adev->gfx.mec2_fw->data + in gfx_v8_0_cp_compute_load_microcode()
3438 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); in gfx_v8_0_cp_compute_load_microcode()
3705 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) in gfx_v8_0_cp_compute_fini() argument
3709 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_compute_fini()
3710 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_compute_fini()
3715 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); in gfx_v8_0_cp_compute_fini()
3726 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) in gfx_v8_0_cp_compute_resume() argument
3739 mutex_lock(&adev->srbm_mutex); in gfx_v8_0_cp_compute_resume()
3740 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { in gfx_v8_0_cp_compute_resume()
3744 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); in gfx_v8_0_cp_compute_resume()
3747 vi_srbm_select(adev, me, pipe, 0, 0); in gfx_v8_0_cp_compute_resume()
3762 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_cp_compute_resume()
3763 mutex_unlock(&adev->srbm_mutex); in gfx_v8_0_cp_compute_resume()
3766 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_compute_resume()
3767 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_compute_resume()
3770 r = amdgpu_bo_create(adev, in gfx_v8_0_cp_compute_resume()
3776 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); in gfx_v8_0_cp_compute_resume()
3783 gfx_v8_0_cp_compute_fini(adev); in gfx_v8_0_cp_compute_resume()
3789 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); in gfx_v8_0_cp_compute_resume()
3790 gfx_v8_0_cp_compute_fini(adev); in gfx_v8_0_cp_compute_resume()
3795 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); in gfx_v8_0_cp_compute_resume()
3796 gfx_v8_0_cp_compute_fini(adev); in gfx_v8_0_cp_compute_resume()
3812 mutex_lock(&adev->srbm_mutex); in gfx_v8_0_cp_compute_resume()
3813 vi_srbm_select(adev, ring->me, in gfx_v8_0_cp_compute_resume()
3843 for (j = 0; j < adev->usec_timeout; j++) { in gfx_v8_0_cp_compute_resume()
3889 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v8_0_cp_compute_resume()
3899 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v8_0_cp_compute_resume()
3908 if ((adev->asic_type == CHIP_CARRIZO) || in gfx_v8_0_cp_compute_resume()
3909 (adev->asic_type == CHIP_FIJI) || in gfx_v8_0_cp_compute_resume()
3910 (adev->asic_type == CHIP_STONEY)) { in gfx_v8_0_cp_compute_resume()
3949 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_cp_compute_resume()
3950 mutex_unlock(&adev->srbm_mutex); in gfx_v8_0_cp_compute_resume()
3962 r = gfx_v8_0_cp_compute_start(adev); in gfx_v8_0_cp_compute_resume()
3966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_compute_resume()
3967 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_cp_compute_resume()
3978 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) in gfx_v8_0_cp_resume() argument
3982 if (!(adev->flags & AMD_IS_APU)) in gfx_v8_0_cp_resume()
3983 gfx_v8_0_enable_gui_idle_interrupt(adev, false); in gfx_v8_0_cp_resume()
3985 if (!adev->firmware.smu_load) { in gfx_v8_0_cp_resume()
3987 r = gfx_v8_0_cp_gfx_load_microcode(adev); in gfx_v8_0_cp_resume()
3991 r = gfx_v8_0_cp_compute_load_microcode(adev); in gfx_v8_0_cp_resume()
3995 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, in gfx_v8_0_cp_resume()
4000 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, in gfx_v8_0_cp_resume()
4005 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, in gfx_v8_0_cp_resume()
4010 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, in gfx_v8_0_cp_resume()
4016 r = gfx_v8_0_cp_gfx_resume(adev); in gfx_v8_0_cp_resume()
4020 r = gfx_v8_0_cp_compute_resume(adev); in gfx_v8_0_cp_resume()
4024 gfx_v8_0_enable_gui_idle_interrupt(adev, true); in gfx_v8_0_cp_resume()
4029 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) in gfx_v8_0_cp_enable() argument
4031 gfx_v8_0_cp_gfx_enable(adev, enable); in gfx_v8_0_cp_enable()
4032 gfx_v8_0_cp_compute_enable(adev, enable); in gfx_v8_0_cp_enable()
4038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_hw_init() local
4040 gfx_v8_0_init_golden_registers(adev); in gfx_v8_0_hw_init()
4042 gfx_v8_0_gpu_init(adev); in gfx_v8_0_hw_init()
4044 r = gfx_v8_0_rlc_resume(adev); in gfx_v8_0_hw_init()
4048 r = gfx_v8_0_cp_resume(adev); in gfx_v8_0_hw_init()
4057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_hw_fini() local
4059 gfx_v8_0_cp_enable(adev, false); in gfx_v8_0_hw_fini()
4060 gfx_v8_0_rlc_stop(adev); in gfx_v8_0_hw_fini()
4061 gfx_v8_0_cp_compute_fini(adev); in gfx_v8_0_hw_fini()
4068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_suspend() local
4070 return gfx_v8_0_hw_fini(adev); in gfx_v8_0_suspend()
4075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_resume() local
4077 return gfx_v8_0_hw_init(adev); in gfx_v8_0_resume()
4082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_is_idle() local
4094 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_wait_for_idle() local
4096 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v8_0_wait_for_idle()
4110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_print_status() local
4112 dev_info(adev->dev, "GFX 8.x registers\n"); in gfx_v8_0_print_status()
4113 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", in gfx_v8_0_print_status()
4115 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", in gfx_v8_0_print_status()
4117 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", in gfx_v8_0_print_status()
4119 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", in gfx_v8_0_print_status()
4121 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", in gfx_v8_0_print_status()
4123 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", in gfx_v8_0_print_status()
4125 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); in gfx_v8_0_print_status()
4126 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", in gfx_v8_0_print_status()
4128 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", in gfx_v8_0_print_status()
4130 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", in gfx_v8_0_print_status()
4132 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", in gfx_v8_0_print_status()
4134 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", in gfx_v8_0_print_status()
4136 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); in gfx_v8_0_print_status()
4137 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); in gfx_v8_0_print_status()
4138 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", in gfx_v8_0_print_status()
4140 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); in gfx_v8_0_print_status()
4143 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", in gfx_v8_0_print_status()
4147 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", in gfx_v8_0_print_status()
4150 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_print_status()
4151 dev_info(adev->dev, " se: %d\n", i); in gfx_v8_0_print_status()
4152 gfx_v8_0_select_se_sh(adev, i, 0xffffffff); in gfx_v8_0_print_status()
4153 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4155 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", in gfx_v8_0_print_status()
4158 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v8_0_print_status()
4160 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4162 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4164 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", in gfx_v8_0_print_status()
4166 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4168 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4170 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4172 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4174 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4177 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", in gfx_v8_0_print_status()
4179 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", in gfx_v8_0_print_status()
4181 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", in gfx_v8_0_print_status()
4183 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4185 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4187 dev_info(adev->dev, " DB_DEBUG=0x%08X\n", in gfx_v8_0_print_status()
4189 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", in gfx_v8_0_print_status()
4191 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", in gfx_v8_0_print_status()
4193 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", in gfx_v8_0_print_status()
4195 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", in gfx_v8_0_print_status()
4197 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", in gfx_v8_0_print_status()
4199 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", in gfx_v8_0_print_status()
4201 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4203 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", in gfx_v8_0_print_status()
4205 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", in gfx_v8_0_print_status()
4207 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", in gfx_v8_0_print_status()
4209 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", in gfx_v8_0_print_status()
4211 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", in gfx_v8_0_print_status()
4213 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", in gfx_v8_0_print_status()
4216 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4218 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", in gfx_v8_0_print_status()
4220 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", in gfx_v8_0_print_status()
4222 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", in gfx_v8_0_print_status()
4225 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", in gfx_v8_0_print_status()
4228 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", in gfx_v8_0_print_status()
4230 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", in gfx_v8_0_print_status()
4232 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4234 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", in gfx_v8_0_print_status()
4236 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", in gfx_v8_0_print_status()
4238 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", in gfx_v8_0_print_status()
4240 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4242 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", in gfx_v8_0_print_status()
4244 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", in gfx_v8_0_print_status()
4246 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4248 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", in gfx_v8_0_print_status()
4251 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", in gfx_v8_0_print_status()
4253 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", in gfx_v8_0_print_status()
4256 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", in gfx_v8_0_print_status()
4258 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4260 dev_info(adev->dev, " RLC_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4262 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", in gfx_v8_0_print_status()
4264 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", in gfx_v8_0_print_status()
4266 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", in gfx_v8_0_print_status()
4268 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", in gfx_v8_0_print_status()
4270 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", in gfx_v8_0_print_status()
4272 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4274 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4276 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", in gfx_v8_0_print_status()
4279 mutex_lock(&adev->srbm_mutex); in gfx_v8_0_print_status()
4281 vi_srbm_select(adev, 0, 0, 0, i); in gfx_v8_0_print_status()
4282 dev_info(adev->dev, " VM %d:\n", i); in gfx_v8_0_print_status()
4283 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", in gfx_v8_0_print_status()
4285 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", in gfx_v8_0_print_status()
4287 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", in gfx_v8_0_print_status()
4289 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", in gfx_v8_0_print_status()
4292 vi_srbm_select(adev, 0, 0, 0, 0); in gfx_v8_0_print_status()
4293 mutex_unlock(&adev->srbm_mutex); in gfx_v8_0_print_status()
4300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_soft_reset() local
4336 gfx_v8_0_print_status((void *)adev); in gfx_v8_0_soft_reset()
4338 gfx_v8_0_rlc_stop(adev); in gfx_v8_0_soft_reset()
4341 gfx_v8_0_cp_gfx_enable(adev, false); in gfx_v8_0_soft_reset()
4349 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v8_0_soft_reset()
4363 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v8_0_soft_reset()
4375 gfx_v8_0_print_status((void *)adev); in gfx_v8_0_soft_reset()
4388 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) in gfx_v8_0_get_gpu_clock_counter() argument
4392 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
4396 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v8_0_get_gpu_clock_counter()
4450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v8_0_early_init() local
4452 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; in gfx_v8_0_early_init()
4453 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; in gfx_v8_0_early_init()
4454 gfx_v8_0_set_ring_funcs(adev); in gfx_v8_0_early_init()
4455 gfx_v8_0_set_irq_funcs(adev); in gfx_v8_0_early_init()
4456 gfx_v8_0_set_gds_init(adev); in gfx_v8_0_early_init()
4477 rptr = ring->adev->wb.wb[ring->rptr_offs]; in gfx_v8_0_ring_get_rptr_gfx()
4484 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_get_wptr_gfx() local
4489 wptr = ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_gfx()
4498 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_set_wptr_gfx() local
4502 adev->wb.wb[ring->wptr_offs] = ring->wptr; in gfx_v8_0_ring_set_wptr_gfx()
4654 if (ring->adev->asic_type == CHIP_TOPAZ || in gfx_v8_0_ring_emit_semaphore()
4655 ring->adev->asic_type == CHIP_TONGA || in gfx_v8_0_ring_emit_semaphore()
4656 ring->adev->asic_type == CHIP_FIJI) in gfx_v8_0_ring_emit_semaphore()
4748 return ring->adev->wb.wb[ring->rptr_offs]; in gfx_v8_0_ring_get_rptr_compute()
4753 return ring->adev->wb.wb[ring->wptr_offs]; in gfx_v8_0_ring_get_wptr_compute()
4758 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_set_wptr_compute() local
4761 adev->wb.wb[ring->wptr_offs] = ring->wptr; in gfx_v8_0_ring_set_wptr_compute()
4786 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v8_0_set_gfx_eop_interrupt_state() argument
4810 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v8_0_set_compute_eop_interrupt_state() argument
4854 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, in gfx_v8_0_set_priv_reg_fault_state() argument
4881 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, in gfx_v8_0_set_priv_inst_fault_state() argument
4908 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v8_0_set_eop_interrupt_state() argument
4915 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); in gfx_v8_0_set_eop_interrupt_state()
4918 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v8_0_set_eop_interrupt_state()
4921 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); in gfx_v8_0_set_eop_interrupt_state()
4924 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); in gfx_v8_0_set_eop_interrupt_state()
4927 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); in gfx_v8_0_set_eop_interrupt_state()
4930 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v8_0_set_eop_interrupt_state()
4933 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); in gfx_v8_0_set_eop_interrupt_state()
4936 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); in gfx_v8_0_set_eop_interrupt_state()
4939 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); in gfx_v8_0_set_eop_interrupt_state()
4947 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, in gfx_v8_0_eop_irq() argument
4962 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v8_0_eop_irq()
4966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()
4967 ring = &adev->gfx.compute_ring[i]; in gfx_v8_0_eop_irq()
4979 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, in gfx_v8_0_priv_reg_irq() argument
4984 schedule_work(&adev->reset_work); in gfx_v8_0_priv_reg_irq()
4988 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, in gfx_v8_0_priv_inst_irq() argument
4993 schedule_work(&adev->reset_work); in gfx_v8_0_priv_inst_irq()
5046 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) in gfx_v8_0_set_ring_funcs() argument
5050 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v8_0_set_ring_funcs()
5051 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; in gfx_v8_0_set_ring_funcs()
5053 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_set_ring_funcs()
5054 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; in gfx_v8_0_set_ring_funcs()
5072 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) in gfx_v8_0_set_irq_funcs() argument
5074 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
5075 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; in gfx_v8_0_set_irq_funcs()
5077 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
5078 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; in gfx_v8_0_set_irq_funcs()
5080 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
5081 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; in gfx_v8_0_set_irq_funcs()
5084 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) in gfx_v8_0_set_gds_init() argument
5087 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v8_0_set_gds_init()
5088 adev->gds.gws.total_size = 64; in gfx_v8_0_set_gds_init()
5089 adev->gds.oa.total_size = 16; in gfx_v8_0_set_gds_init()
5091 if (adev->gds.mem.total_size == 64 * 1024) { in gfx_v8_0_set_gds_init()
5092 adev->gds.mem.gfx_partition_size = 4096; in gfx_v8_0_set_gds_init()
5093 adev->gds.mem.cs_partition_size = 4096; in gfx_v8_0_set_gds_init()
5095 adev->gds.gws.gfx_partition_size = 4; in gfx_v8_0_set_gds_init()
5096 adev->gds.gws.cs_partition_size = 4; in gfx_v8_0_set_gds_init()
5098 adev->gds.oa.gfx_partition_size = 4; in gfx_v8_0_set_gds_init()
5099 adev->gds.oa.cs_partition_size = 1; in gfx_v8_0_set_gds_init()
5101 adev->gds.mem.gfx_partition_size = 1024; in gfx_v8_0_set_gds_init()
5102 adev->gds.mem.cs_partition_size = 1024; in gfx_v8_0_set_gds_init()
5104 adev->gds.gws.gfx_partition_size = 16; in gfx_v8_0_set_gds_init()
5105 adev->gds.gws.cs_partition_size = 16; in gfx_v8_0_set_gds_init()
5107 adev->gds.oa.gfx_partition_size = 4; in gfx_v8_0_set_gds_init()
5108 adev->gds.oa.cs_partition_size = 4; in gfx_v8_0_set_gds_init()
5112 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev, in gfx_v8_0_get_cu_active_bitmap() argument
5118 gfx_v8_0_select_se_sh(adev, se, sh); in gfx_v8_0_get_cu_active_bitmap()
5121 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v8_0_get_cu_active_bitmap()
5128 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { in gfx_v8_0_get_cu_active_bitmap()
5136 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, in gfx_v8_0_get_cu_info() argument
5142 if (!adev || !cu_info) in gfx_v8_0_get_cu_info()
5145 mutex_lock(&adev->grbm_idx_mutex); in gfx_v8_0_get_cu_info()
5146 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v8_0_get_cu_info()
5147 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_get_cu_info()
5151 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j); in gfx_v8_0_get_cu_info()
5154 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v8_0_get_cu_info()
5169 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v8_0_get_cu_info()