633 	WREG32(scratch, 0xCAFEDEAD);  in gfx_v8_0_ring_test_ring()
679 	WREG32(scratch, 0xCAFEDEAD);  in gfx_v8_0_ring_test_ib()
1512 			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
1608 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
1802 			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
1898 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2093 			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2189 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2360 			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2456 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2628 			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2724 			WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);  in gfx_v8_0_tiling_mode_table_init()
2757 	WREG32(mmGRBM_GFX_INDEX, data);  in gfx_v8_0_select_se_sh()
2839 		WREG32(mmPA_SC_RASTER_CONFIG, data);  in gfx_v8_0_setup_rb()
2881 		WREG32(mmSH_MEM_CONFIG, sh_mem_config);  in gfx_v8_0_init_compute_vmid()
2882 		WREG32(mmSH_MEM_APE1_BASE, 1);  in gfx_v8_0_init_compute_vmid()
2883 		WREG32(mmSH_MEM_APE1_LIMIT, 0);  in gfx_v8_0_init_compute_vmid()
2884 		WREG32(mmSH_MEM_BASES, sh_mem_bases);  in gfx_v8_0_init_compute_vmid()
2897 	WREG32(mmGRBM_CNTL, tmp);  in gfx_v8_0_gpu_init()
2899 	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2900 	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2901 	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2902 	WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,  in gfx_v8_0_gpu_init()
2904 	WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,  in gfx_v8_0_gpu_init()
2906 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2907 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2908 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2927 			WREG32(mmSH_MEM_CONFIG, tmp);  in gfx_v8_0_gpu_init()
2933 			WREG32(mmSH_MEM_CONFIG, tmp);  in gfx_v8_0_gpu_init()
2936 		WREG32(mmSH_MEM_APE1_BASE, 1);  in gfx_v8_0_gpu_init()
2937 		WREG32(mmSH_MEM_APE1_LIMIT, 0);  in gfx_v8_0_gpu_init()
2938 		WREG32(mmSH_MEM_BASES, 0);  in gfx_v8_0_gpu_init()
2952 	WREG32(mmPA_SC_FIFO_SIZE,  in gfx_v8_0_gpu_init()
3011 	WREG32(mmCP_INT_CNTL_RING0, tmp);  in gfx_v8_0_enable_gui_idle_interrupt()
3019 	WREG32(mmRLC_CNTL, tmp);  in gfx_v8_0_rlc_stop()
3031 	WREG32(mmGRBM_SOFT_RESET, tmp);  in gfx_v8_0_rlc_reset()
3034 	WREG32(mmGRBM_SOFT_RESET, tmp);  in gfx_v8_0_rlc_reset()
3043 	WREG32(mmRLC_CNTL, tmp);  in gfx_v8_0_rlc_start()
3068 	WREG32(mmRLC_GPM_UCODE_ADDR, 0);  in gfx_v8_0_rlc_load_microcode()
3070 		WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));  in gfx_v8_0_rlc_load_microcode()
3071 	WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v8_0_rlc_load_microcode()
3083 	WREG32(mmRLC_CGCG_CGLS_CTRL, 0);  in gfx_v8_0_rlc_resume()
3086 	WREG32(mmRLC_PG_CNTL, 0);  in gfx_v8_0_rlc_resume()
3123 	WREG32(mmCP_ME_CNTL, tmp);  in gfx_v8_0_cp_gfx_enable()
3156 	WREG32(mmCP_PFP_UCODE_ADDR, 0);  in gfx_v8_0_cp_gfx_load_microcode()
3158 		WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));  in gfx_v8_0_cp_gfx_load_microcode()
3159 	WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);  in gfx_v8_0_cp_gfx_load_microcode()
3166 	WREG32(mmCP_CE_UCODE_ADDR, 0);  in gfx_v8_0_cp_gfx_load_microcode()
3168 		WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));  in gfx_v8_0_cp_gfx_load_microcode()
3169 	WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);  in gfx_v8_0_cp_gfx_load_microcode()
3176 	WREG32(mmCP_ME_RAM_WADDR, 0);  in gfx_v8_0_cp_gfx_load_microcode()
3178 		WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));  in gfx_v8_0_cp_gfx_load_microcode()
3179 	WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);  in gfx_v8_0_cp_gfx_load_microcode()
3221 	WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);  in gfx_v8_0_cp_gfx_start()
3222 	WREG32(mmCP_ENDIAN_SWAP, 0);  in gfx_v8_0_cp_gfx_start()
3223 	WREG32(mmCP_DEVICE_ID, 1);  in gfx_v8_0_cp_gfx_start()
3305 	WREG32(mmCP_RB_WPTR_DELAY, 0);  in gfx_v8_0_cp_gfx_resume()
3308 	WREG32(mmCP_RB_VMID, 0);  in gfx_v8_0_cp_gfx_resume()
3320 	WREG32(mmCP_RB0_CNTL, tmp);  in gfx_v8_0_cp_gfx_resume()
3323 	WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);  in gfx_v8_0_cp_gfx_resume()
3325 	WREG32(mmCP_RB0_WPTR, ring->wptr);  in gfx_v8_0_cp_gfx_resume()
3329 	WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));  in gfx_v8_0_cp_gfx_resume()
3330 	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);  in gfx_v8_0_cp_gfx_resume()
3333 	WREG32(mmCP_RB0_CNTL, tmp);  in gfx_v8_0_cp_gfx_resume()
3336 	WREG32(mmCP_RB0_BASE, rb_addr);  in gfx_v8_0_cp_gfx_resume()
3337 	WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));  in gfx_v8_0_cp_gfx_resume()
3351 		WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);  in gfx_v8_0_cp_gfx_resume()
3357 			WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);  in gfx_v8_0_cp_gfx_resume()
3359 			WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,  in gfx_v8_0_cp_gfx_resume()
3382 		WREG32(mmCP_MEC_CNTL, 0);  in gfx_v8_0_cp_compute_enable()
3384 		WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));  in gfx_v8_0_cp_compute_enable()
3418 	WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);  in gfx_v8_0_cp_compute_load_microcode()
3420 		WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));  in gfx_v8_0_cp_compute_load_microcode()
3421 	WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);  in gfx_v8_0_cp_compute_load_microcode()
3435 		WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);  in gfx_v8_0_cp_compute_load_microcode()
3437 			WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));  in gfx_v8_0_cp_compute_load_microcode()
3438 		WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);  in gfx_v8_0_cp_compute_load_microcode()
3750 		WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);  in gfx_v8_0_cp_compute_resume()
3751 		WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));  in gfx_v8_0_cp_compute_resume()
3754 		WREG32(mmCP_HQD_VMID, 0);  in gfx_v8_0_cp_compute_resume()
3760 		WREG32(mmCP_HQD_EOP_CONTROL, tmp);  in gfx_v8_0_cp_compute_resume()
3820 		WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);  in gfx_v8_0_cp_compute_resume()
3834 		WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);  in gfx_v8_0_cp_compute_resume()
3842 			WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);  in gfx_v8_0_cp_compute_resume()
3848 			WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);  in gfx_v8_0_cp_compute_resume()
3849 			WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);  in gfx_v8_0_cp_compute_resume()
3850 			WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);  in gfx_v8_0_cp_compute_resume()
3856 		WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);  in gfx_v8_0_cp_compute_resume()
3857 		WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);  in gfx_v8_0_cp_compute_resume()
3862 		WREG32(mmCP_MQD_CONTROL, tmp);  in gfx_v8_0_cp_compute_resume()
3869 		WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);  in gfx_v8_0_cp_compute_resume()
3870 		WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);  in gfx_v8_0_cp_compute_resume()
3885 		WREG32(mmCP_HQD_PQ_CONTROL, tmp);  in gfx_v8_0_cp_compute_resume()
3893 		WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,  in gfx_v8_0_cp_compute_resume()
3895 		WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,  in gfx_v8_0_cp_compute_resume()
3902 		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);  in gfx_v8_0_cp_compute_resume()
3903 		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,  in gfx_v8_0_cp_compute_resume()
3911 				WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,  in gfx_v8_0_cp_compute_resume()
3913 				WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,  in gfx_v8_0_cp_compute_resume()
3927 		WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,  in gfx_v8_0_cp_compute_resume()
3933 		WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);  in gfx_v8_0_cp_compute_resume()
3938 		WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);  in gfx_v8_0_cp_compute_resume()
3942 		WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);  in gfx_v8_0_cp_compute_resume()
3947 		WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);  in gfx_v8_0_cp_compute_resume()
3959 		WREG32(mmCP_PQ_STATUS, tmp);  in gfx_v8_0_cp_compute_resume()
4350 			WREG32(mmGRBM_SOFT_RESET, tmp);  in gfx_v8_0_soft_reset()
4356 			WREG32(mmGRBM_SOFT_RESET, tmp);  in gfx_v8_0_soft_reset()
4364 			WREG32(mmSRBM_SOFT_RESET, tmp);  in gfx_v8_0_soft_reset()
4370 			WREG32(mmSRBM_SOFT_RESET, tmp);  in gfx_v8_0_soft_reset()
4393 	WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);  in gfx_v8_0_get_gpu_clock_counter()
4505 		WREG32(mmCP_RB0_WPTR, ring->wptr);  in gfx_v8_0_ring_set_wptr_gfx()
4796 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v8_0_set_gfx_eop_interrupt_state()
4803 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v8_0_set_gfx_eop_interrupt_state()
4841 		WREG32(mec_int_cntl_reg, mec_int_cntl);  in gfx_v8_0_set_compute_eop_interrupt_state()
4847 		WREG32(mec_int_cntl_reg, mec_int_cntl);  in gfx_v8_0_set_compute_eop_interrupt_state()
4866 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v8_0_set_priv_reg_fault_state()
4872 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v8_0_set_priv_reg_fault_state()
4893 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v8_0_set_priv_inst_fault_state()
4899 		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);  in gfx_v8_0_set_priv_inst_fault_state()