2865 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_cp_gfx_start()
3708 	if (adev->gfx.rlc.save_restore_obj) {  in gfx_v7_0_rlc_fini()
3709 		r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);  in gfx_v7_0_rlc_fini()
3712 		amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_fini()
3713 		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_fini()
3715 		amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_fini()
3716 		adev->gfx.rlc.save_restore_obj = NULL;  in gfx_v7_0_rlc_fini()
3720 	if (adev->gfx.rlc.clear_state_obj) {  in gfx_v7_0_rlc_fini()
3721 		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);  in gfx_v7_0_rlc_fini()
3724 		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_fini()
3725 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_fini()
3727 		amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_fini()
3728 		adev->gfx.rlc.clear_state_obj = NULL;  in gfx_v7_0_rlc_fini()
3732 	if (adev->gfx.rlc.cp_table_obj) {  in gfx_v7_0_rlc_fini()
3733 		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);  in gfx_v7_0_rlc_fini()
3736 		amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_fini()
3737 		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_fini()
3739 		amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_fini()
3740 		adev->gfx.rlc.cp_table_obj = NULL;  in gfx_v7_0_rlc_fini()
3755 			adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3756 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3759 			adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3760 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3764 	adev->gfx.rlc.cs_data = ci_cs_data;  in gfx_v7_0_rlc_init()
3765 	adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;  in gfx_v7_0_rlc_init()
3767 	src_ptr = adev->gfx.rlc.reg_list;  in gfx_v7_0_rlc_init()
3768 	dws = adev->gfx.rlc.reg_list_size;  in gfx_v7_0_rlc_init()
3771 	cs_data = adev->gfx.rlc.cs_data;  in gfx_v7_0_rlc_init()
3775 		if (adev->gfx.rlc.save_restore_obj == NULL) {  in gfx_v7_0_rlc_init()
3780 					     &adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3787 		r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);  in gfx_v7_0_rlc_init()
3792 		r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,  in gfx_v7_0_rlc_init()
3793 				  &adev->gfx.rlc.save_restore_gpu_addr);  in gfx_v7_0_rlc_init()
3795 			amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3801 		r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);  in gfx_v7_0_rlc_init()
3808 		dst_ptr = adev->gfx.rlc.sr_ptr;  in gfx_v7_0_rlc_init()
3809 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v7_0_rlc_init()
3811 		amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3812 		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3817 		adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);  in gfx_v7_0_rlc_init()
3819 		if (adev->gfx.rlc.clear_state_obj == NULL) {  in gfx_v7_0_rlc_init()
3824 					     &adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3831 		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);  in gfx_v7_0_rlc_init()
3836 		r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,  in gfx_v7_0_rlc_init()
3837 				  &adev->gfx.rlc.clear_state_gpu_addr);  in gfx_v7_0_rlc_init()
3839 			amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3845 		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);  in gfx_v7_0_rlc_init()
3852 		dst_ptr = adev->gfx.rlc.cs_ptr;  in gfx_v7_0_rlc_init()
3854 		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3855 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3858 	if (adev->gfx.rlc.cp_table_size) {  in gfx_v7_0_rlc_init()
3859 		if (adev->gfx.rlc.cp_table_obj == NULL) {  in gfx_v7_0_rlc_init()
3860 			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,  in gfx_v7_0_rlc_init()
3864 					     &adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3872 		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);  in gfx_v7_0_rlc_init()
3878 		r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,  in gfx_v7_0_rlc_init()
3879 				  &adev->gfx.rlc.cp_table_gpu_addr);  in gfx_v7_0_rlc_init()
3881 			amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3886 		r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);  in gfx_v7_0_rlc_init()
3895 		amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3896 		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3945 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)  in gfx_v7_0_update_rlc()  argument
3950 	if (tmp != rlc)  in gfx_v7_0_update_rlc()
3951 		WREG32(mmRLC_CNTL, rlc);  in gfx_v7_0_update_rlc()
4324 	if (adev->gfx.rlc.cp_table_ptr == NULL)  in gfx_v7_0_init_cp_pg_table()
4328 	dst_ptr = adev->gfx.rlc.cp_table_ptr;  in gfx_v7_0_init_cp_pg_table()
4488 	if (adev->gfx.rlc.cs_data) {  in gfx_v7_0_init_gfx_cgpg()
4490 		WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
4491 		WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
4492 		WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);  in gfx_v7_0_init_gfx_cgpg()
4498 	if (adev->gfx.rlc.reg_list) {  in gfx_v7_0_init_gfx_cgpg()
4500 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v7_0_init_gfx_cgpg()
4501 			WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);  in gfx_v7_0_init_gfx_cgpg()
4509 	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
4510 	WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
4545 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_size()
4553 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_size()
4578 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_buffer()
4590 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_buffer()