Lines Matching refs:ring
2368 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) in gfx_v7_0_ring_test_ring() argument
2370 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_test_ring()
2382 r = amdgpu_ring_lock(ring, 3); in gfx_v7_0_ring_test_ring()
2384 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); in gfx_v7_0_ring_test_ring()
2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2389 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); in gfx_v7_0_ring_test_ring()
2390 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2391 amdgpu_ring_unlock_commit(ring); in gfx_v7_0_ring_test_ring()
2400 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in gfx_v7_0_ring_test_ring()
2403 ring->idx, scratch, tmp); in gfx_v7_0_ring_test_ring()
2418 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) in gfx_v7_0_ring_emit_hdp_flush() argument
2421 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; in gfx_v7_0_ring_emit_hdp_flush()
2423 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { in gfx_v7_0_ring_emit_hdp_flush()
2424 switch (ring->me) { in gfx_v7_0_ring_emit_hdp_flush()
2426 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2429 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2438 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2439 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in gfx_v7_0_ring_emit_hdp_flush()
2442 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); in gfx_v7_0_ring_emit_hdp_flush()
2443 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); in gfx_v7_0_ring_emit_hdp_flush()
2444 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2445 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2446 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
2458 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, in gfx_v7_0_ring_emit_fence_gfx() argument
2466 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2467 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | in gfx_v7_0_ring_emit_fence_gfx()
2471 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_gfx()
2472 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v7_0_ring_emit_fence_gfx()
2474 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); in gfx_v7_0_ring_emit_fence_gfx()
2475 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); in gfx_v7_0_ring_emit_fence_gfx()
2478 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2479 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | in gfx_v7_0_ring_emit_fence_gfx()
2483 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_gfx()
2484 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v7_0_ring_emit_fence_gfx()
2486 amdgpu_ring_write(ring, lower_32_bits(seq)); in gfx_v7_0_ring_emit_fence_gfx()
2487 amdgpu_ring_write(ring, upper_32_bits(seq)); in gfx_v7_0_ring_emit_fence_gfx()
2499 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, in gfx_v7_0_ring_emit_fence_compute() argument
2507 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2508 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | in gfx_v7_0_ring_emit_fence_compute()
2512 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
2513 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_compute()
2514 amdgpu_ring_write(ring, upper_32_bits(addr)); in gfx_v7_0_ring_emit_fence_compute()
2515 amdgpu_ring_write(ring, lower_32_bits(seq)); in gfx_v7_0_ring_emit_fence_compute()
2516 amdgpu_ring_write(ring, upper_32_bits(seq)); in gfx_v7_0_ring_emit_fence_compute()
2529 static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring, in gfx_v7_0_ring_emit_semaphore() argument
2536 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in gfx_v7_0_ring_emit_semaphore()
2537 amdgpu_ring_write(ring, addr & 0xffffffff); in gfx_v7_0_ring_emit_semaphore()
2538 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in gfx_v7_0_ring_emit_semaphore()
2540 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { in gfx_v7_0_ring_emit_semaphore()
2542 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v7_0_ring_emit_semaphore()
2543 amdgpu_ring_write(ring, 0x0); in gfx_v7_0_ring_emit_semaphore()
2564 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, in gfx_v7_0_ring_emit_ib_gfx() argument
2567 bool need_ctx_switch = ring->current_ctx != ib->ctx; in gfx_v7_0_ring_emit_ib_gfx()
2569 u32 next_rptr = ring->wptr + 5; in gfx_v7_0_ring_emit_ib_gfx()
2579 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_ib_gfx()
2580 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v7_0_ring_emit_ib_gfx()
2581 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in gfx_v7_0_ring_emit_ib_gfx()
2582 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); in gfx_v7_0_ring_emit_ib_gfx()
2583 amdgpu_ring_write(ring, next_rptr); in gfx_v7_0_ring_emit_ib_gfx()
2587 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2588 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_ib_gfx()
2597 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); in gfx_v7_0_ring_emit_ib_gfx()
2599 amdgpu_ring_write(ring, header); in gfx_v7_0_ring_emit_ib_gfx()
2600 amdgpu_ring_write(ring, in gfx_v7_0_ring_emit_ib_gfx()
2605 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v7_0_ring_emit_ib_gfx()
2606 amdgpu_ring_write(ring, control); in gfx_v7_0_ring_emit_ib_gfx()
2609 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, in gfx_v7_0_ring_emit_ib_compute() argument
2613 u32 next_rptr = ring->wptr + 5; in gfx_v7_0_ring_emit_ib_compute()
2617 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_ib_compute()
2618 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v7_0_ring_emit_ib_compute()
2619 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in gfx_v7_0_ring_emit_ib_compute()
2620 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); in gfx_v7_0_ring_emit_ib_compute()
2621 amdgpu_ring_write(ring, next_rptr); in gfx_v7_0_ring_emit_ib_compute()
2626 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); in gfx_v7_0_ring_emit_ib_compute()
2628 amdgpu_ring_write(ring, header); in gfx_v7_0_ring_emit_ib_compute()
2629 amdgpu_ring_write(ring, in gfx_v7_0_ring_emit_ib_compute()
2634 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v7_0_ring_emit_ib_compute()
2635 amdgpu_ring_write(ring, control); in gfx_v7_0_ring_emit_ib_compute()
2647 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring) in gfx_v7_0_ring_test_ib() argument
2649 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_test_ib()
2664 r = amdgpu_ib_get(ring, NULL, 256, &ib); in gfx_v7_0_ring_test_ib()
2674 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL, in gfx_v7_0_ring_test_ib()
2693 ring->idx, i); in gfx_v7_0_ring_test_ib()
2833 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start() local
2845 r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8); in gfx_v7_0_cp_gfx_start()
2852 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start()
2853 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in gfx_v7_0_cp_gfx_start()
2854 amdgpu_ring_write(ring, 0x8000); in gfx_v7_0_cp_gfx_start()
2855 amdgpu_ring_write(ring, 0x8000); in gfx_v7_0_cp_gfx_start()
2858 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2859 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
2861 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v7_0_cp_gfx_start()
2862 amdgpu_ring_write(ring, 0x80000000); in gfx_v7_0_cp_gfx_start()
2863 amdgpu_ring_write(ring, 0x80000000); in gfx_v7_0_cp_gfx_start()
2868 amdgpu_ring_write(ring, in gfx_v7_0_cp_gfx_start()
2870 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
2872 amdgpu_ring_write(ring, ext->extent[i]); in gfx_v7_0_cp_gfx_start()
2877 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
2878 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
2881 amdgpu_ring_write(ring, 0x16000012); in gfx_v7_0_cp_gfx_start()
2882 amdgpu_ring_write(ring, 0x00000000); in gfx_v7_0_cp_gfx_start()
2885 amdgpu_ring_write(ring, 0x00000000); /* XXX */ in gfx_v7_0_cp_gfx_start()
2886 amdgpu_ring_write(ring, 0x00000000); in gfx_v7_0_cp_gfx_start()
2890 amdgpu_ring_write(ring, 0x00000000); /* XXX */ in gfx_v7_0_cp_gfx_start()
2891 amdgpu_ring_write(ring, 0x00000000); in gfx_v7_0_cp_gfx_start()
2894 amdgpu_ring_write(ring, 0x3a00161a); in gfx_v7_0_cp_gfx_start()
2895 amdgpu_ring_write(ring, 0x0000002e); in gfx_v7_0_cp_gfx_start()
2898 amdgpu_ring_write(ring, 0x00000000); in gfx_v7_0_cp_gfx_start()
2899 amdgpu_ring_write(ring, 0x00000000); in gfx_v7_0_cp_gfx_start()
2903 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2904 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
2906 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
2907 amdgpu_ring_write(ring, 0); in gfx_v7_0_cp_gfx_start()
2909 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
2910 amdgpu_ring_write(ring, 0x00000316); in gfx_v7_0_cp_gfx_start()
2911 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in gfx_v7_0_cp_gfx_start()
2912 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in gfx_v7_0_cp_gfx_start()
2914 amdgpu_ring_unlock_commit(ring); in gfx_v7_0_cp_gfx_start()
2930 struct amdgpu_ring *ring; in gfx_v7_0_cp_gfx_resume() local
2950 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2951 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v7_0_cp_gfx_resume()
2960 ring->wptr = 0; in gfx_v7_0_cp_gfx_resume()
2961 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v7_0_cp_gfx_resume()
2964 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_cp_gfx_resume()
2974 rb_addr = ring->gpu_addr >> 8; in gfx_v7_0_cp_gfx_resume()
2980 ring->ready = true; in gfx_v7_0_cp_gfx_resume()
2981 r = amdgpu_ring_test_ring(ring); in gfx_v7_0_cp_gfx_resume()
2983 ring->ready = false; in gfx_v7_0_cp_gfx_resume()
2990 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) in gfx_v7_0_ring_get_rptr_gfx() argument
2994 rptr = ring->adev->wb.wb[ring->rptr_offs]; in gfx_v7_0_ring_get_rptr_gfx()
2999 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) in gfx_v7_0_ring_get_wptr_gfx() argument
3001 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_get_wptr_gfx()
3009 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) in gfx_v7_0_ring_set_wptr_gfx() argument
3011 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_set_wptr_gfx()
3013 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v7_0_ring_set_wptr_gfx()
3017 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring) in gfx_v7_0_ring_get_rptr_compute() argument
3021 rptr = ring->adev->wb.wb[ring->rptr_offs]; in gfx_v7_0_ring_get_rptr_compute()
3026 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) in gfx_v7_0_ring_get_wptr_compute() argument
3031 wptr = ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
3036 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) in gfx_v7_0_ring_set_wptr_compute() argument
3038 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_set_wptr_compute()
3041 adev->wb.wb[ring->wptr_offs] = ring->wptr; in gfx_v7_0_ring_set_wptr_compute()
3042 WDOORBELL32(ring->doorbell_index, ring->wptr); in gfx_v7_0_ring_set_wptr_compute()
3156 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini() local
3158 if (ring->mqd_obj) { in gfx_v7_0_cp_compute_fini()
3159 r = amdgpu_bo_reserve(ring->mqd_obj, false); in gfx_v7_0_cp_compute_fini()
3163 amdgpu_bo_unpin(ring->mqd_obj); in gfx_v7_0_cp_compute_fini()
3164 amdgpu_bo_unreserve(ring->mqd_obj); in gfx_v7_0_cp_compute_fini()
3166 amdgpu_bo_unref(&ring->mqd_obj); in gfx_v7_0_cp_compute_fini()
3167 ring->mqd_obj = NULL; in gfx_v7_0_cp_compute_fini()
3370 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume() local
3372 if (ring->mqd_obj == NULL) { in gfx_v7_0_cp_compute_resume()
3377 &ring->mqd_obj); in gfx_v7_0_cp_compute_resume()
3384 r = amdgpu_bo_reserve(ring->mqd_obj, false); in gfx_v7_0_cp_compute_resume()
3389 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, in gfx_v7_0_cp_compute_resume()
3396 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); in gfx_v7_0_cp_compute_resume()
3414 cik_srbm_select(adev, ring->me, in gfx_v7_0_cp_compute_resume()
3415 ring->pipe, in gfx_v7_0_cp_compute_resume()
3416 ring->queue, 0); in gfx_v7_0_cp_compute_resume()
3460 hqd_gpu_addr = ring->gpu_addr >> 8; in gfx_v7_0_cp_compute_resume()
3473 order_base_2(ring->ring_size / 8); in gfx_v7_0_cp_compute_resume()
3490 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_cp_compute_resume()
3498 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_cp_compute_resume()
3514 (ring->doorbell_index << in gfx_v7_0_cp_compute_resume()
3529 ring->wptr = 0; in gfx_v7_0_cp_compute_resume()
3530 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; in gfx_v7_0_cp_compute_resume()
3545 amdgpu_bo_kunmap(ring->mqd_obj); in gfx_v7_0_cp_compute_resume()
3546 amdgpu_bo_unreserve(ring->mqd_obj); in gfx_v7_0_cp_compute_resume()
3548 ring->ready = true; in gfx_v7_0_cp_compute_resume()
3549 r = amdgpu_ring_test_ring(ring); in gfx_v7_0_cp_compute_resume()
3551 ring->ready = false; in gfx_v7_0_cp_compute_resume()
3627 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, in gfx_v7_0_ring_emit_vm_flush() argument
3630 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); in gfx_v7_0_ring_emit_vm_flush()
3631 uint32_t seq = ring->fence_drv.sync_seq[ring->idx]; in gfx_v7_0_ring_emit_vm_flush()
3632 uint64_t addr = ring->fence_drv.gpu_addr; in gfx_v7_0_ring_emit_vm_flush()
3634 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
3635 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ in gfx_v7_0_ring_emit_vm_flush()
3638 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_vm_flush()
3639 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v7_0_ring_emit_vm_flush()
3640 amdgpu_ring_write(ring, seq); in gfx_v7_0_ring_emit_vm_flush()
3641 amdgpu_ring_write(ring, 0xffffffff); in gfx_v7_0_ring_emit_vm_flush()
3642 amdgpu_ring_write(ring, 4); /* poll interval */ in gfx_v7_0_ring_emit_vm_flush()
3646 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3647 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3648 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3649 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3652 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_vm_flush()
3653 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in gfx_v7_0_ring_emit_vm_flush()
3656 amdgpu_ring_write(ring, in gfx_v7_0_ring_emit_vm_flush()
3659 amdgpu_ring_write(ring, in gfx_v7_0_ring_emit_vm_flush()
3662 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3663 amdgpu_ring_write(ring, pd_addr >> 12); in gfx_v7_0_ring_emit_vm_flush()
3666 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_vm_flush()
3667 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_vm_flush()
3669 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); in gfx_v7_0_ring_emit_vm_flush()
3670 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3671 amdgpu_ring_write(ring, 1 << vm_id); in gfx_v7_0_ring_emit_vm_flush()
3674 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
3675 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in gfx_v7_0_ring_emit_vm_flush()
3678 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); in gfx_v7_0_ring_emit_vm_flush()
3679 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3680 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v7_0_ring_emit_vm_flush()
3681 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v7_0_ring_emit_vm_flush()
3682 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_vm_flush()
3687 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v7_0_ring_emit_vm_flush()
3688 amdgpu_ring_write(ring, 0x0); in gfx_v7_0_ring_emit_vm_flush()
3691 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3692 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3693 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3694 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
4693 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, in gfx_v7_0_ring_emit_gds_switch() argument
4709 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4710 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4712 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); in gfx_v7_0_ring_emit_gds_switch()
4713 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4714 amdgpu_ring_write(ring, gds_base); in gfx_v7_0_ring_emit_gds_switch()
4717 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4718 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4720 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); in gfx_v7_0_ring_emit_gds_switch()
4721 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4722 amdgpu_ring_write(ring, gds_size); in gfx_v7_0_ring_emit_gds_switch()
4725 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4726 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4728 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); in gfx_v7_0_ring_emit_gds_switch()
4729 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4730 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); in gfx_v7_0_ring_emit_gds_switch()
4733 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4734 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
4736 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); in gfx_v7_0_ring_emit_gds_switch()
4737 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4738 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); in gfx_v7_0_ring_emit_gds_switch()
4756 struct amdgpu_ring *ring; in gfx_v7_0_sw_init() local
4797 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4798 ring->ring_obj = NULL; in gfx_v7_0_sw_init()
4799 sprintf(ring->name, "gfx"); in gfx_v7_0_sw_init()
4800 r = amdgpu_ring_init(adev, ring, 1024 * 1024, in gfx_v7_0_sw_init()
4817 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_sw_init()
4818 ring->ring_obj = NULL; in gfx_v7_0_sw_init()
4819 ring->use_doorbell = true; in gfx_v7_0_sw_init()
4820 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; in gfx_v7_0_sw_init()
4821 ring->me = 1; /* first MEC */ in gfx_v7_0_sw_init()
4822 ring->pipe = i / 8; in gfx_v7_0_sw_init()
4823 ring->queue = i % 8; in gfx_v7_0_sw_init()
4824 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); in gfx_v7_0_sw_init()
4825 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; in gfx_v7_0_sw_init()
4827 r = amdgpu_ring_init(adev, ring, 1024 * 1024, in gfx_v7_0_sw_init()
5452 struct amdgpu_ring *ring; in gfx_v7_0_eop_irq() local
5465 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
5466 if ((ring->me == me_id) & (ring->pipe == pipe_id)) in gfx_v7_0_eop_irq()
5467 amdgpu_fence_process(ring); in gfx_v7_0_eop_irq()