928 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);  in gfx_v7_0_init_microcode()
931 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);  in gfx_v7_0_init_microcode()
936 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);  in gfx_v7_0_init_microcode()
939 	err = amdgpu_ucode_validate(adev->gfx.me_fw);  in gfx_v7_0_init_microcode()
944 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);  in gfx_v7_0_init_microcode()
947 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);  in gfx_v7_0_init_microcode()
952 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);  in gfx_v7_0_init_microcode()
955 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);  in gfx_v7_0_init_microcode()
961 		err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);  in gfx_v7_0_init_microcode()
964 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);  in gfx_v7_0_init_microcode()
970 	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);  in gfx_v7_0_init_microcode()
973 	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);  in gfx_v7_0_init_microcode()
980 		release_firmware(adev->gfx.pfp_fw);  in gfx_v7_0_init_microcode()
981 		adev->gfx.pfp_fw = NULL;  in gfx_v7_0_init_microcode()
982 		release_firmware(adev->gfx.me_fw);  in gfx_v7_0_init_microcode()
983 		adev->gfx.me_fw = NULL;  in gfx_v7_0_init_microcode()
984 		release_firmware(adev->gfx.ce_fw);  in gfx_v7_0_init_microcode()
985 		adev->gfx.ce_fw = NULL;  in gfx_v7_0_init_microcode()
986 		release_firmware(adev->gfx.mec_fw);  in gfx_v7_0_init_microcode()
987 		adev->gfx.mec_fw = NULL;  in gfx_v7_0_init_microcode()
988 		release_firmware(adev->gfx.mec2_fw);  in gfx_v7_0_init_microcode()
989 		adev->gfx.mec2_fw = NULL;  in gfx_v7_0_init_microcode()
990 		release_firmware(adev->gfx.rlc_fw);  in gfx_v7_0_init_microcode()
991 		adev->gfx.rlc_fw = NULL;  in gfx_v7_0_init_microcode()
1013 	switch (adev->gfx.config.mem_row_size_in_kb) {  in gfx_v7_0_tiling_mode_table_init()
1199 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v7_0_tiling_mode_table_init()
1292 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v7_0_tiling_mode_table_init()
1484 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v7_0_tiling_mode_table_init()
1577 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v7_0_tiling_mode_table_init()
1756 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v7_0_tiling_mode_table_init()
1849 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v7_0_tiling_mode_table_init()
1977 	adev->gfx.config.backend_enable_mask = enabled_rbs;  in gfx_v7_0_setup_rb()
2071 		adev->gfx.config.max_shader_engines = 2;  in gfx_v7_0_gpu_init()
2072 		adev->gfx.config.max_tile_pipes = 4;  in gfx_v7_0_gpu_init()
2073 		adev->gfx.config.max_cu_per_sh = 7;  in gfx_v7_0_gpu_init()
2074 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v7_0_gpu_init()
2075 		adev->gfx.config.max_backends_per_se = 2;  in gfx_v7_0_gpu_init()
2076 		adev->gfx.config.max_texture_channel_caches = 4;  in gfx_v7_0_gpu_init()
2077 		adev->gfx.config.max_gprs = 256;  in gfx_v7_0_gpu_init()
2078 		adev->gfx.config.max_gs_threads = 32;  in gfx_v7_0_gpu_init()
2079 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v7_0_gpu_init()
2081 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v7_0_gpu_init()
2082 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v7_0_gpu_init()
2083 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v7_0_gpu_init()
2084 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v7_0_gpu_init()
2088 		adev->gfx.config.max_shader_engines = 4;  in gfx_v7_0_gpu_init()
2089 		adev->gfx.config.max_tile_pipes = 16;  in gfx_v7_0_gpu_init()
2090 		adev->gfx.config.max_cu_per_sh = 11;  in gfx_v7_0_gpu_init()
2091 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v7_0_gpu_init()
2092 		adev->gfx.config.max_backends_per_se = 4;  in gfx_v7_0_gpu_init()
2093 		adev->gfx.config.max_texture_channel_caches = 16;  in gfx_v7_0_gpu_init()
2094 		adev->gfx.config.max_gprs = 256;  in gfx_v7_0_gpu_init()
2095 		adev->gfx.config.max_gs_threads = 32;  in gfx_v7_0_gpu_init()
2096 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v7_0_gpu_init()
2098 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v7_0_gpu_init()
2099 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v7_0_gpu_init()
2100 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v7_0_gpu_init()
2101 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v7_0_gpu_init()
2105 		adev->gfx.config.max_shader_engines = 1;  in gfx_v7_0_gpu_init()
2106 		adev->gfx.config.max_tile_pipes = 4;  in gfx_v7_0_gpu_init()
2114 			adev->gfx.config.max_cu_per_sh = 8;  in gfx_v7_0_gpu_init()
2115 			adev->gfx.config.max_backends_per_se = 2;  in gfx_v7_0_gpu_init()
2121 			adev->gfx.config.max_cu_per_sh = 6;  in gfx_v7_0_gpu_init()
2122 			adev->gfx.config.max_backends_per_se = 2;  in gfx_v7_0_gpu_init()
2129 			adev->gfx.config.max_cu_per_sh = 4;  in gfx_v7_0_gpu_init()
2130 			adev->gfx.config.max_backends_per_se = 1;  in gfx_v7_0_gpu_init()
2132 			adev->gfx.config.max_cu_per_sh = 3;  in gfx_v7_0_gpu_init()
2133 			adev->gfx.config.max_backends_per_se = 1;  in gfx_v7_0_gpu_init()
2135 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v7_0_gpu_init()
2136 		adev->gfx.config.max_texture_channel_caches = 4;  in gfx_v7_0_gpu_init()
2137 		adev->gfx.config.max_gprs = 256;  in gfx_v7_0_gpu_init()
2138 		adev->gfx.config.max_gs_threads = 16;  in gfx_v7_0_gpu_init()
2139 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v7_0_gpu_init()
2141 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v7_0_gpu_init()
2142 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v7_0_gpu_init()
2143 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v7_0_gpu_init()
2144 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v7_0_gpu_init()
2150 		adev->gfx.config.max_shader_engines = 1;  in gfx_v7_0_gpu_init()
2151 		adev->gfx.config.max_tile_pipes = 2;  in gfx_v7_0_gpu_init()
2152 		adev->gfx.config.max_cu_per_sh = 2;  in gfx_v7_0_gpu_init()
2153 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v7_0_gpu_init()
2154 		adev->gfx.config.max_backends_per_se = 1;  in gfx_v7_0_gpu_init()
2155 		adev->gfx.config.max_texture_channel_caches = 2;  in gfx_v7_0_gpu_init()
2156 		adev->gfx.config.max_gprs = 256;  in gfx_v7_0_gpu_init()
2157 		adev->gfx.config.max_gs_threads = 16;  in gfx_v7_0_gpu_init()
2158 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v7_0_gpu_init()
2160 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v7_0_gpu_init()
2161 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v7_0_gpu_init()
2162 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v7_0_gpu_init()
2163 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v7_0_gpu_init()
2171 	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);  in gfx_v7_0_gpu_init()
2172 	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;  in gfx_v7_0_gpu_init()
2174 	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;  in gfx_v7_0_gpu_init()
2175 	adev->gfx.config.mem_max_burst_length_bytes = 256;  in gfx_v7_0_gpu_init()
2199 			adev->gfx.config.mem_row_size_in_kb = 2;  in gfx_v7_0_gpu_init()
2201 			adev->gfx.config.mem_row_size_in_kb = 1;  in gfx_v7_0_gpu_init()
2204 		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;  in gfx_v7_0_gpu_init()
2205 		if (adev->gfx.config.mem_row_size_in_kb > 4)  in gfx_v7_0_gpu_init()
2206 			adev->gfx.config.mem_row_size_in_kb = 4;  in gfx_v7_0_gpu_init()
2209 	adev->gfx.config.shader_engine_tile_size = 32;  in gfx_v7_0_gpu_init()
2210 	adev->gfx.config.num_gpus = 1;  in gfx_v7_0_gpu_init()
2211 	adev->gfx.config.multi_gpu_tile_size = 64;  in gfx_v7_0_gpu_init()
2215 	switch (adev->gfx.config.mem_row_size_in_kb) {  in gfx_v7_0_gpu_init()
2227 	adev->gfx.config.gb_addr_config = gb_addr_config;  in gfx_v7_0_gpu_init()
2240 	gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines,  in gfx_v7_0_gpu_init()
2241 			  adev->gfx.config.max_sh_per_se,  in gfx_v7_0_gpu_init()
2242 			  adev->gfx.config.max_backends_per_se);  in gfx_v7_0_gpu_init()
2302 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF…  in gfx_v7_0_gpu_init()
2303 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |  in gfx_v7_0_gpu_init()
2304 		(adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |  in gfx_v7_0_gpu_init()
2305 		(adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));  in gfx_v7_0_gpu_init()
2349 	adev->gfx.scratch.num_reg = 7;  in gfx_v7_0_scratch_init()
2350 	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;  in gfx_v7_0_scratch_init()
2351 	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {  in gfx_v7_0_scratch_init()
2352 		adev->gfx.scratch.free[i] = true;  in gfx_v7_0_scratch_init()
2353 		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;  in gfx_v7_0_scratch_init()
2748 		for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v7_0_cp_gfx_enable()
2749 			adev->gfx.gfx_ring[i].ready = false;  in gfx_v7_0_cp_gfx_enable()
2770 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)  in gfx_v7_0_cp_gfx_load_microcode()
2773 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;  in gfx_v7_0_cp_gfx_load_microcode()
2774 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;  in gfx_v7_0_cp_gfx_load_microcode()
2775 	me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;  in gfx_v7_0_cp_gfx_load_microcode()
2780 	adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);  in gfx_v7_0_cp_gfx_load_microcode()
2781 	adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);  in gfx_v7_0_cp_gfx_load_microcode()
2782 	adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);  in gfx_v7_0_cp_gfx_load_microcode()
2783 	adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);  in gfx_v7_0_cp_gfx_load_microcode()
2784 	adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);  in gfx_v7_0_cp_gfx_load_microcode()
2785 	adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);  in gfx_v7_0_cp_gfx_load_microcode()
2791 		(adev->gfx.pfp_fw->data +  in gfx_v7_0_cp_gfx_load_microcode()
2797 	WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);  in gfx_v7_0_cp_gfx_load_microcode()
2801 		(adev->gfx.ce_fw->data +  in gfx_v7_0_cp_gfx_load_microcode()
2807 	WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);  in gfx_v7_0_cp_gfx_load_microcode()
2811 		(adev->gfx.me_fw->data +  in gfx_v7_0_cp_gfx_load_microcode()
2817 	WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);  in gfx_v7_0_cp_gfx_load_microcode()
2833 	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];  in gfx_v7_0_cp_gfx_start()
2839 	WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);  in gfx_v7_0_cp_gfx_start()
2865 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_cp_gfx_start()
2950 	ring = &adev->gfx.gfx_ring[0];  in gfx_v7_0_cp_gfx_resume()
3061 		for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v7_0_cp_compute_enable()
3062 			adev->gfx.compute_ring[i].ready = false;  in gfx_v7_0_cp_compute_enable()
3081 	if (!adev->gfx.mec_fw)  in gfx_v7_0_cp_compute_load_microcode()
3084 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;  in gfx_v7_0_cp_compute_load_microcode()
3086 	adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);  in gfx_v7_0_cp_compute_load_microcode()
3087 	adev->gfx.mec_feature_version = le32_to_cpu(  in gfx_v7_0_cp_compute_load_microcode()
3094 		(adev->gfx.mec_fw->data +  in gfx_v7_0_cp_compute_load_microcode()
3105 		if (!adev->gfx.mec2_fw)  in gfx_v7_0_cp_compute_load_microcode()
3108 		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;  in gfx_v7_0_cp_compute_load_microcode()
3110 		adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);  in gfx_v7_0_cp_compute_load_microcode()
3111 		adev->gfx.mec2_feature_version = le32_to_cpu(  in gfx_v7_0_cp_compute_load_microcode()
3116 			(adev->gfx.mec2_fw->data +  in gfx_v7_0_cp_compute_load_microcode()
3155 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v7_0_cp_compute_fini()
3156 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];  in gfx_v7_0_cp_compute_fini()
3176 	if (adev->gfx.mec.hpd_eop_obj) {  in gfx_v7_0_mec_fini()
3177 		r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);  in gfx_v7_0_mec_fini()
3180 		amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_fini()
3181 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_fini()
3183 		amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_fini()
3184 		adev->gfx.mec.hpd_eop_obj = NULL;  in gfx_v7_0_mec_fini()
3201 	adev->gfx.mec.num_mec = 1;  in gfx_v7_0_mec_init()
3202 	adev->gfx.mec.num_pipe = 1;  in gfx_v7_0_mec_init()
3203 	adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;  in gfx_v7_0_mec_init()
3205 	if (adev->gfx.mec.hpd_eop_obj == NULL) {  in gfx_v7_0_mec_init()
3207 				     adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,  in gfx_v7_0_mec_init()
3210 				     &adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
3217 	r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);  in gfx_v7_0_mec_init()
3222 	r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,  in gfx_v7_0_mec_init()
3223 			  &adev->gfx.mec.hpd_eop_gpu_addr);  in gfx_v7_0_mec_init()
3229 	r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);  in gfx_v7_0_mec_init()
3237 	memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);  in gfx_v7_0_mec_init()
3239 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
3240 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
3344 	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {  in gfx_v7_0_cp_compute_resume()
3348 		eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);  in gfx_v7_0_cp_compute_resume()
3369 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v7_0_cp_compute_resume()
3370 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];  in gfx_v7_0_cp_compute_resume()
3708 	if (adev->gfx.rlc.save_restore_obj) {  in gfx_v7_0_rlc_fini()
3709 		r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);  in gfx_v7_0_rlc_fini()
3712 		amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_fini()
3713 		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_fini()
3715 		amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_fini()
3716 		adev->gfx.rlc.save_restore_obj = NULL;  in gfx_v7_0_rlc_fini()
3720 	if (adev->gfx.rlc.clear_state_obj) {  in gfx_v7_0_rlc_fini()
3721 		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);  in gfx_v7_0_rlc_fini()
3724 		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_fini()
3725 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_fini()
3727 		amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_fini()
3728 		adev->gfx.rlc.clear_state_obj = NULL;  in gfx_v7_0_rlc_fini()
3732 	if (adev->gfx.rlc.cp_table_obj) {  in gfx_v7_0_rlc_fini()
3733 		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);  in gfx_v7_0_rlc_fini()
3736 		amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_fini()
3737 		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_fini()
3739 		amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_fini()
3740 		adev->gfx.rlc.cp_table_obj = NULL;  in gfx_v7_0_rlc_fini()
3755 			adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3756 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3759 			adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3760 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3764 	adev->gfx.rlc.cs_data = ci_cs_data;  in gfx_v7_0_rlc_init()
3765 	adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;  in gfx_v7_0_rlc_init()
3767 	src_ptr = adev->gfx.rlc.reg_list;  in gfx_v7_0_rlc_init()
3768 	dws = adev->gfx.rlc.reg_list_size;  in gfx_v7_0_rlc_init()
3771 	cs_data = adev->gfx.rlc.cs_data;  in gfx_v7_0_rlc_init()
3775 		if (adev->gfx.rlc.save_restore_obj == NULL) {  in gfx_v7_0_rlc_init()
3780 					     &adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3787 		r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);  in gfx_v7_0_rlc_init()
3792 		r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,  in gfx_v7_0_rlc_init()
3793 				  &adev->gfx.rlc.save_restore_gpu_addr);  in gfx_v7_0_rlc_init()
3795 			amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3801 		r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);  in gfx_v7_0_rlc_init()
3808 		dst_ptr = adev->gfx.rlc.sr_ptr;  in gfx_v7_0_rlc_init()
3809 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v7_0_rlc_init()
3811 		amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3812 		amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);  in gfx_v7_0_rlc_init()
3817 		adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);  in gfx_v7_0_rlc_init()
3819 		if (adev->gfx.rlc.clear_state_obj == NULL) {  in gfx_v7_0_rlc_init()
3824 					     &adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3831 		r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);  in gfx_v7_0_rlc_init()
3836 		r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,  in gfx_v7_0_rlc_init()
3837 				  &adev->gfx.rlc.clear_state_gpu_addr);  in gfx_v7_0_rlc_init()
3839 			amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3845 		r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);  in gfx_v7_0_rlc_init()
3852 		dst_ptr = adev->gfx.rlc.cs_ptr;  in gfx_v7_0_rlc_init()
3854 		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3855 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v7_0_rlc_init()
3858 	if (adev->gfx.rlc.cp_table_size) {  in gfx_v7_0_rlc_init()
3859 		if (adev->gfx.rlc.cp_table_obj == NULL) {  in gfx_v7_0_rlc_init()
3860 			r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,  in gfx_v7_0_rlc_init()
3864 					     &adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3872 		r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);  in gfx_v7_0_rlc_init()
3878 		r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,  in gfx_v7_0_rlc_init()
3879 				  &adev->gfx.rlc.cp_table_gpu_addr);  in gfx_v7_0_rlc_init()
3881 			amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3886 		r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);  in gfx_v7_0_rlc_init()
3895 		amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3896 		amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);  in gfx_v7_0_rlc_init()
3921 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v7_0_wait_for_rlc_serdes()
3922 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v7_0_wait_for_rlc_serdes()
4068 	if (!adev->gfx.rlc_fw)  in gfx_v7_0_rlc_resume()
4071 	hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;  in gfx_v7_0_rlc_resume()
4073 	adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);  in gfx_v7_0_rlc_resume()
4074 	adev->gfx.rlc_feature_version = le32_to_cpu(  in gfx_v7_0_rlc_resume()
4101 		(adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in gfx_v7_0_rlc_resume()
4106 	WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v7_0_rlc_resume()
4324 	if (adev->gfx.rlc.cp_table_ptr == NULL)  in gfx_v7_0_init_cp_pg_table()
4328 	dst_ptr = adev->gfx.rlc.cp_table_ptr;  in gfx_v7_0_init_cp_pg_table()
4332 				(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;  in gfx_v7_0_init_cp_pg_table()
4334 				(adev->gfx.ce_fw->data +  in gfx_v7_0_init_cp_pg_table()
4340 				(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;  in gfx_v7_0_init_cp_pg_table()
4342 				(adev->gfx.pfp_fw->data +  in gfx_v7_0_init_cp_pg_table()
4348 				(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;  in gfx_v7_0_init_cp_pg_table()
4350 				(adev->gfx.me_fw->data +  in gfx_v7_0_init_cp_pg_table()
4356 				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;  in gfx_v7_0_init_cp_pg_table()
4358 				(adev->gfx.mec_fw->data +  in gfx_v7_0_init_cp_pg_table()
4364 				(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;  in gfx_v7_0_init_cp_pg_table()
4366 				(adev->gfx.mec2_fw->data +  in gfx_v7_0_init_cp_pg_table()
4427 	for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {  in gfx_v7_0_get_cu_active_bitmap()
4488 	if (adev->gfx.rlc.cs_data) {  in gfx_v7_0_init_gfx_cgpg()
4490 		WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
4491 		WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
4492 		WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);  in gfx_v7_0_init_gfx_cgpg()
4498 	if (adev->gfx.rlc.reg_list) {  in gfx_v7_0_init_gfx_cgpg()
4500 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v7_0_init_gfx_cgpg()
4501 			WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);  in gfx_v7_0_init_gfx_cgpg()
4509 	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
4510 	WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
4545 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_size()
4553 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_size()
4578 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_buffer()
4590 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_buffer()
4685 	mutex_lock(&adev->gfx.gpu_clock_mutex);  in gfx_v7_0_get_gpu_clock_counter()
4689 	mutex_unlock(&adev->gfx.gpu_clock_mutex);  in gfx_v7_0_get_gpu_clock_counter()
4745 	adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;  in gfx_v7_0_early_init()
4746 	adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;  in gfx_v7_0_early_init()
4761 	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);  in gfx_v7_0_sw_init()
4766 	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);  in gfx_v7_0_sw_init()
4771 	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);  in gfx_v7_0_sw_init()
4796 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v7_0_sw_init()
4797 		ring = &adev->gfx.gfx_ring[i];  in gfx_v7_0_sw_init()
4802 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,  in gfx_v7_0_sw_init()
4809 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v7_0_sw_init()
4817 		ring = &adev->gfx.compute_ring[i];  in gfx_v7_0_sw_init()
4829 				     &adev->gfx.eop_irq, irq_type,  in gfx_v7_0_sw_init()
4869 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v7_0_sw_fini()
4870 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);  in gfx_v7_0_sw_fini()
4871 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v7_0_sw_fini()
4872 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);  in gfx_v7_0_sw_fini()
4897 	adev->gfx.ce_ram_size = 0x8000;  in gfx_v7_0_hw_init()
4997 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v7_0_print_status()
5108 	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {  in gfx_v7_0_print_status()
5460 		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);  in gfx_v7_0_eop_irq()
5464 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v7_0_eop_irq()
5465 			ring = &adev->gfx.compute_ring[i];  in gfx_v7_0_eop_irq()
5594 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v7_0_set_ring_funcs()
5595 		adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;  in gfx_v7_0_set_ring_funcs()
5596 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v7_0_set_ring_funcs()
5597 		adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;  in gfx_v7_0_set_ring_funcs()
5617 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;  in gfx_v7_0_set_irq_funcs()
5618 	adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;  in gfx_v7_0_set_irq_funcs()
5620 	adev->gfx.priv_reg_irq.num_types = 1;  in gfx_v7_0_set_irq_funcs()
5621 	adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;  in gfx_v7_0_set_irq_funcs()
5623 	adev->gfx.priv_inst_irq.num_types = 1;  in gfx_v7_0_set_irq_funcs()
5624 	adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;  in gfx_v7_0_set_irq_funcs()
5666 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v7_0_get_cu_info()
5667 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v7_0_get_cu_info()
5674 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {  in gfx_v7_0_get_cu_info()