Lines Matching refs:adev
55 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
56 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
57 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
900 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) in gfx_v7_0_init_microcode() argument
908 switch (adev->asic_type) { in gfx_v7_0_init_microcode()
928 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
931 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
936 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
939 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
944 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
947 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
952 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
955 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
959 if (adev->asic_type == CHIP_KAVERI) { in gfx_v7_0_init_microcode()
961 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
964 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
970 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
973 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
980 release_firmware(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
981 adev->gfx.pfp_fw = NULL; in gfx_v7_0_init_microcode()
982 release_firmware(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
983 adev->gfx.me_fw = NULL; in gfx_v7_0_init_microcode()
984 release_firmware(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
985 adev->gfx.ce_fw = NULL; in gfx_v7_0_init_microcode()
986 release_firmware(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
987 adev->gfx.mec_fw = NULL; in gfx_v7_0_init_microcode()
988 release_firmware(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
989 adev->gfx.mec2_fw = NULL; in gfx_v7_0_init_microcode()
990 release_firmware(adev->gfx.rlc_fw); in gfx_v7_0_init_microcode()
991 adev->gfx.rlc_fw = NULL; in gfx_v7_0_init_microcode()
1007 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) in gfx_v7_0_tiling_mode_table_init() argument
1013 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_tiling_mode_table_init()
1026 switch (adev->asic_type) { in gfx_v7_0_tiling_mode_table_init()
1199 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v7_0_tiling_mode_table_init()
1292 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v7_0_tiling_mode_table_init()
1484 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v7_0_tiling_mode_table_init()
1577 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v7_0_tiling_mode_table_init()
1756 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; in gfx_v7_0_tiling_mode_table_init()
1849 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; in gfx_v7_0_tiling_mode_table_init()
1867 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) in gfx_v7_0_select_se_sh() argument
1916 static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev, in gfx_v7_0_get_rb_disabled() argument
1947 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev, in gfx_v7_0_setup_rb() argument
1956 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_setup_rb()
1959 gfx_v7_0_select_se_sh(adev, i, j); in gfx_v7_0_setup_rb()
1960 data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se); in gfx_v7_0_setup_rb()
1961 if (adev->asic_type == CHIP_HAWAII) in gfx_v7_0_setup_rb()
1967 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_setup_rb()
1968 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_setup_rb()
1977 adev->gfx.config.backend_enable_mask = enabled_rbs; in gfx_v7_0_setup_rb()
1979 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_setup_rb()
1981 gfx_v7_0_select_se_sh(adev, i, 0xffffffff); in gfx_v7_0_setup_rb()
2008 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_setup_rb()
2009 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_setup_rb()
2023 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) in gmc_v7_0_init_compute_vmid() argument
2039 mutex_lock(&adev->srbm_mutex); in gmc_v7_0_init_compute_vmid()
2041 cik_srbm_select(adev, 0, 0, 0, i); in gmc_v7_0_init_compute_vmid()
2048 cik_srbm_select(adev, 0, 0, 0, 0); in gmc_v7_0_init_compute_vmid()
2049 mutex_unlock(&adev->srbm_mutex); in gmc_v7_0_init_compute_vmid()
2060 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) in gfx_v7_0_gpu_init() argument
2069 switch (adev->asic_type) { in gfx_v7_0_gpu_init()
2071 adev->gfx.config.max_shader_engines = 2; in gfx_v7_0_gpu_init()
2072 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_init()
2073 adev->gfx.config.max_cu_per_sh = 7; in gfx_v7_0_gpu_init()
2074 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_init()
2075 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_init()
2076 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_init()
2077 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_init()
2078 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_init()
2079 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_init()
2081 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_init()
2082 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_init()
2083 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_init()
2084 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_init()
2088 adev->gfx.config.max_shader_engines = 4; in gfx_v7_0_gpu_init()
2089 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_init()
2090 adev->gfx.config.max_cu_per_sh = 11; in gfx_v7_0_gpu_init()
2091 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_init()
2092 adev->gfx.config.max_backends_per_se = 4; in gfx_v7_0_gpu_init()
2093 adev->gfx.config.max_texture_channel_caches = 16; in gfx_v7_0_gpu_init()
2094 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_init()
2095 adev->gfx.config.max_gs_threads = 32; in gfx_v7_0_gpu_init()
2096 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_init()
2098 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_init()
2099 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_init()
2100 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_init()
2101 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_init()
2105 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_init()
2106 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_init()
2107 if ((adev->pdev->device == 0x1304) || in gfx_v7_0_gpu_init()
2108 (adev->pdev->device == 0x1305) || in gfx_v7_0_gpu_init()
2109 (adev->pdev->device == 0x130C) || in gfx_v7_0_gpu_init()
2110 (adev->pdev->device == 0x130F) || in gfx_v7_0_gpu_init()
2111 (adev->pdev->device == 0x1310) || in gfx_v7_0_gpu_init()
2112 (adev->pdev->device == 0x1311) || in gfx_v7_0_gpu_init()
2113 (adev->pdev->device == 0x131C)) { in gfx_v7_0_gpu_init()
2114 adev->gfx.config.max_cu_per_sh = 8; in gfx_v7_0_gpu_init()
2115 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_init()
2116 } else if ((adev->pdev->device == 0x1309) || in gfx_v7_0_gpu_init()
2117 (adev->pdev->device == 0x130A) || in gfx_v7_0_gpu_init()
2118 (adev->pdev->device == 0x130D) || in gfx_v7_0_gpu_init()
2119 (adev->pdev->device == 0x1313) || in gfx_v7_0_gpu_init()
2120 (adev->pdev->device == 0x131D)) { in gfx_v7_0_gpu_init()
2121 adev->gfx.config.max_cu_per_sh = 6; in gfx_v7_0_gpu_init()
2122 adev->gfx.config.max_backends_per_se = 2; in gfx_v7_0_gpu_init()
2123 } else if ((adev->pdev->device == 0x1306) || in gfx_v7_0_gpu_init()
2124 (adev->pdev->device == 0x1307) || in gfx_v7_0_gpu_init()
2125 (adev->pdev->device == 0x130B) || in gfx_v7_0_gpu_init()
2126 (adev->pdev->device == 0x130E) || in gfx_v7_0_gpu_init()
2127 (adev->pdev->device == 0x1315) || in gfx_v7_0_gpu_init()
2128 (adev->pdev->device == 0x131B)) { in gfx_v7_0_gpu_init()
2129 adev->gfx.config.max_cu_per_sh = 4; in gfx_v7_0_gpu_init()
2130 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_init()
2132 adev->gfx.config.max_cu_per_sh = 3; in gfx_v7_0_gpu_init()
2133 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_init()
2135 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_init()
2136 adev->gfx.config.max_texture_channel_caches = 4; in gfx_v7_0_gpu_init()
2137 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_init()
2138 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_init()
2139 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_init()
2141 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_init()
2142 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_init()
2143 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_init()
2144 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_init()
2150 adev->gfx.config.max_shader_engines = 1; in gfx_v7_0_gpu_init()
2151 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_init()
2152 adev->gfx.config.max_cu_per_sh = 2; in gfx_v7_0_gpu_init()
2153 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_init()
2154 adev->gfx.config.max_backends_per_se = 1; in gfx_v7_0_gpu_init()
2155 adev->gfx.config.max_texture_channel_caches = 2; in gfx_v7_0_gpu_init()
2156 adev->gfx.config.max_gprs = 256; in gfx_v7_0_gpu_init()
2157 adev->gfx.config.max_gs_threads = 16; in gfx_v7_0_gpu_init()
2158 adev->gfx.config.max_hw_contexts = 8; in gfx_v7_0_gpu_init()
2160 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_init()
2161 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_init()
2162 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_init()
2163 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_init()
2171 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_init()
2172 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; in gfx_v7_0_gpu_init()
2174 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_init()
2175 adev->gfx.config.mem_max_burst_length_bytes = 256; in gfx_v7_0_gpu_init()
2176 if (adev->flags & AMD_IS_APU) { in gfx_v7_0_gpu_init()
2199 adev->gfx.config.mem_row_size_in_kb = 2; in gfx_v7_0_gpu_init()
2201 adev->gfx.config.mem_row_size_in_kb = 1; in gfx_v7_0_gpu_init()
2204 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in gfx_v7_0_gpu_init()
2205 if (adev->gfx.config.mem_row_size_in_kb > 4) in gfx_v7_0_gpu_init()
2206 adev->gfx.config.mem_row_size_in_kb = 4; in gfx_v7_0_gpu_init()
2209 adev->gfx.config.shader_engine_tile_size = 32; in gfx_v7_0_gpu_init()
2210 adev->gfx.config.num_gpus = 1; in gfx_v7_0_gpu_init()
2211 adev->gfx.config.multi_gpu_tile_size = 64; in gfx_v7_0_gpu_init()
2215 switch (adev->gfx.config.mem_row_size_in_kb) { in gfx_v7_0_gpu_init()
2227 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v7_0_gpu_init()
2238 gfx_v7_0_tiling_mode_table_init(adev); in gfx_v7_0_gpu_init()
2240 gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines, in gfx_v7_0_gpu_init()
2241 adev->gfx.config.max_sh_per_se, in gfx_v7_0_gpu_init()
2242 adev->gfx.config.max_backends_per_se); in gfx_v7_0_gpu_init()
2249 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_gpu_init()
2254 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_gpu_init()
2261 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_gpu_init()
2263 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_gpu_init()
2270 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_gpu_init()
2271 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_gpu_init()
2273 gmc_v7_0_init_compute_vmid(adev); in gfx_v7_0_gpu_init()
2302 …((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIF… in gfx_v7_0_gpu_init()
2303 …(adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | in gfx_v7_0_gpu_init()
2304 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | in gfx_v7_0_gpu_init()
2305 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); in gfx_v7_0_gpu_init()
2327 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_gpu_init()
2345 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) in gfx_v7_0_scratch_init() argument
2349 adev->gfx.scratch.num_reg = 7; in gfx_v7_0_scratch_init()
2350 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v7_0_scratch_init()
2351 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { in gfx_v7_0_scratch_init()
2352 adev->gfx.scratch.free[i] = true; in gfx_v7_0_scratch_init()
2353 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; in gfx_v7_0_scratch_init()
2370 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_test_ring() local
2376 r = amdgpu_gfx_scratch_get(adev, &scratch); in gfx_v7_0_ring_test_ring()
2385 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v7_0_ring_test_ring()
2393 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_ring_test_ring()
2399 if (i < adev->usec_timeout) { in gfx_v7_0_ring_test_ring()
2406 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v7_0_ring_test_ring()
2649 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_test_ib() local
2657 r = amdgpu_gfx_scratch_get(adev, &scratch); in gfx_v7_0_ring_test_ib()
2674 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL, in gfx_v7_0_ring_test_ib()
2685 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_ring_test_ib()
2691 if (i < adev->usec_timeout) { in gfx_v7_0_ring_test_ib()
2703 amdgpu_ib_free(adev, &ib); in gfx_v7_0_ring_test_ib()
2705 amdgpu_gfx_scratch_free(adev, scratch); in gfx_v7_0_ring_test_ib()
2740 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) in gfx_v7_0_cp_gfx_enable() argument
2748 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_cp_gfx_enable()
2749 adev->gfx.gfx_ring[i].ready = false; in gfx_v7_0_cp_gfx_enable()
2762 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) in gfx_v7_0_cp_gfx_load_microcode() argument
2770 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v7_0_cp_gfx_load_microcode()
2773 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2774 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2775 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_cp_gfx_load_microcode()
2780 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2781 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2782 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); in gfx_v7_0_cp_gfx_load_microcode()
2783 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2784 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2785 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); in gfx_v7_0_cp_gfx_load_microcode()
2787 gfx_v7_0_cp_gfx_enable(adev, false); in gfx_v7_0_cp_gfx_load_microcode()
2791 (adev->gfx.pfp_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2797 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2801 (adev->gfx.ce_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2807 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2811 (adev->gfx.me_fw->data + in gfx_v7_0_cp_gfx_load_microcode()
2817 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2831 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) in gfx_v7_0_cp_gfx_start() argument
2833 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2839 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2843 gfx_v7_0_cp_gfx_enable(adev, true); in gfx_v7_0_cp_gfx_start()
2845 r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8); in gfx_v7_0_cp_gfx_start()
2865 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
2879 switch (adev->asic_type) { in gfx_v7_0_cp_gfx_start()
2928 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) in gfx_v7_0_cp_gfx_resume() argument
2937 if (adev->asic_type != CHIP_HAWAII) in gfx_v7_0_cp_gfx_resume()
2950 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2964 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_cp_gfx_resume()
2979 gfx_v7_0_cp_gfx_start(adev); in gfx_v7_0_cp_gfx_resume()
2994 rptr = ring->adev->wb.wb[ring->rptr_offs]; in gfx_v7_0_ring_get_rptr_gfx()
3001 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_get_wptr_gfx() local
3011 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_set_wptr_gfx() local
3021 rptr = ring->adev->wb.wb[ring->rptr_offs]; in gfx_v7_0_ring_get_rptr_compute()
3031 wptr = ring->adev->wb.wb[ring->wptr_offs]; in gfx_v7_0_ring_get_wptr_compute()
3038 struct amdgpu_device *adev = ring->adev; in gfx_v7_0_ring_set_wptr_compute() local
3041 adev->wb.wb[ring->wptr_offs] = ring->wptr; in gfx_v7_0_ring_set_wptr_compute()
3053 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) in gfx_v7_0_cp_compute_enable() argument
3061 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_cp_compute_enable()
3062 adev->gfx.compute_ring[i].ready = false; in gfx_v7_0_cp_compute_enable()
3075 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_load_microcode() argument
3081 if (!adev->gfx.mec_fw) in gfx_v7_0_cp_compute_load_microcode()
3084 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_cp_compute_load_microcode()
3086 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
3087 adev->gfx.mec_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
3090 gfx_v7_0_cp_compute_enable(adev, false); in gfx_v7_0_cp_compute_load_microcode()
3094 (adev->gfx.mec_fw->data + in gfx_v7_0_cp_compute_load_microcode()
3102 if (adev->asic_type == CHIP_KAVERI) { in gfx_v7_0_cp_compute_load_microcode()
3105 if (!adev->gfx.mec2_fw) in gfx_v7_0_cp_compute_load_microcode()
3108 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_cp_compute_load_microcode()
3110 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); in gfx_v7_0_cp_compute_load_microcode()
3111 adev->gfx.mec2_feature_version = le32_to_cpu( in gfx_v7_0_cp_compute_load_microcode()
3116 (adev->gfx.mec2_fw->data + in gfx_v7_0_cp_compute_load_microcode()
3136 static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_start() argument
3138 gfx_v7_0_cp_compute_enable(adev, true); in gfx_v7_0_cp_compute_start()
3151 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_fini() argument
3155 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
3156 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_fini()
3161 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); in gfx_v7_0_cp_compute_fini()
3172 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) in gfx_v7_0_mec_fini() argument
3176 if (adev->gfx.mec.hpd_eop_obj) { in gfx_v7_0_mec_fini()
3177 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); in gfx_v7_0_mec_fini()
3179 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); in gfx_v7_0_mec_fini()
3180 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_fini()
3181 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_fini()
3183 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_fini()
3184 adev->gfx.mec.hpd_eop_obj = NULL; in gfx_v7_0_mec_fini()
3190 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) in gfx_v7_0_mec_init() argument
3201 adev->gfx.mec.num_mec = 1; in gfx_v7_0_mec_init()
3202 adev->gfx.mec.num_pipe = 1; in gfx_v7_0_mec_init()
3203 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; in gfx_v7_0_mec_init()
3205 if (adev->gfx.mec.hpd_eop_obj == NULL) { in gfx_v7_0_mec_init()
3206 r = amdgpu_bo_create(adev, in gfx_v7_0_mec_init()
3207 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, in gfx_v7_0_mec_init()
3210 &adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
3212 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); in gfx_v7_0_mec_init()
3217 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); in gfx_v7_0_mec_init()
3219 gfx_v7_0_mec_fini(adev); in gfx_v7_0_mec_init()
3222 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, in gfx_v7_0_mec_init()
3223 &adev->gfx.mec.hpd_eop_gpu_addr); in gfx_v7_0_mec_init()
3225 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); in gfx_v7_0_mec_init()
3226 gfx_v7_0_mec_fini(adev); in gfx_v7_0_mec_init()
3229 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); in gfx_v7_0_mec_init()
3231 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); in gfx_v7_0_mec_init()
3232 gfx_v7_0_mec_fini(adev); in gfx_v7_0_mec_init()
3237 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); in gfx_v7_0_mec_init()
3239 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
3240 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v7_0_mec_init()
3321 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) in gfx_v7_0_cp_compute_resume() argument
3333 r = gfx_v7_0_cp_compute_start(adev); in gfx_v7_0_cp_compute_resume()
3343 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_cp_compute_resume()
3344 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { in gfx_v7_0_cp_compute_resume()
3348 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); in gfx_v7_0_cp_compute_resume()
3350 cik_srbm_select(adev, me, pipe, 0, 0); in gfx_v7_0_cp_compute_resume()
3365 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_cp_compute_resume()
3366 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_cp_compute_resume()
3369 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3370 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_cp_compute_resume()
3373 r = amdgpu_bo_create(adev, in gfx_v7_0_cp_compute_resume()
3379 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); in gfx_v7_0_cp_compute_resume()
3386 gfx_v7_0_cp_compute_fini(adev); in gfx_v7_0_cp_compute_resume()
3392 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); in gfx_v7_0_cp_compute_resume()
3393 gfx_v7_0_cp_compute_fini(adev); in gfx_v7_0_cp_compute_resume()
3398 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); in gfx_v7_0_cp_compute_resume()
3399 gfx_v7_0_cp_compute_fini(adev); in gfx_v7_0_cp_compute_resume()
3413 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_cp_compute_resume()
3414 cik_srbm_select(adev, ring->me, in gfx_v7_0_cp_compute_resume()
3439 for (j = 0; j < adev->usec_timeout; j++) { in gfx_v7_0_cp_compute_resume()
3490 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v7_0_cp_compute_resume()
3498 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in gfx_v7_0_cp_compute_resume()
3542 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_cp_compute_resume()
3543 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_cp_compute_resume()
3557 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) in gfx_v7_0_cp_enable() argument
3559 gfx_v7_0_cp_gfx_enable(adev, enable); in gfx_v7_0_cp_enable()
3560 gfx_v7_0_cp_compute_enable(adev, enable); in gfx_v7_0_cp_enable()
3563 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) in gfx_v7_0_cp_load_microcode() argument
3567 r = gfx_v7_0_cp_gfx_load_microcode(adev); in gfx_v7_0_cp_load_microcode()
3570 r = gfx_v7_0_cp_compute_load_microcode(adev); in gfx_v7_0_cp_load_microcode()
3577 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, in gfx_v7_0_enable_gui_idle_interrupt() argument
3591 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) in gfx_v7_0_cp_resume() argument
3595 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_cp_resume()
3597 r = gfx_v7_0_cp_load_microcode(adev); in gfx_v7_0_cp_resume()
3601 r = gfx_v7_0_cp_gfx_resume(adev); in gfx_v7_0_cp_resume()
3604 r = gfx_v7_0_cp_compute_resume(adev); in gfx_v7_0_cp_resume()
3608 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_cp_resume()
3703 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) in gfx_v7_0_rlc_fini() argument
3708 if (adev->gfx.rlc.save_restore_obj) { in gfx_v7_0_rlc_fini()
3709 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); in gfx_v7_0_rlc_fini()
3711 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); in gfx_v7_0_rlc_fini()
3712 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_fini()
3713 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_fini()
3715 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_fini()
3716 adev->gfx.rlc.save_restore_obj = NULL; in gfx_v7_0_rlc_fini()
3720 if (adev->gfx.rlc.clear_state_obj) { in gfx_v7_0_rlc_fini()
3721 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); in gfx_v7_0_rlc_fini()
3723 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); in gfx_v7_0_rlc_fini()
3724 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_fini()
3725 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_fini()
3727 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_fini()
3728 adev->gfx.rlc.clear_state_obj = NULL; in gfx_v7_0_rlc_fini()
3732 if (adev->gfx.rlc.cp_table_obj) { in gfx_v7_0_rlc_fini()
3733 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); in gfx_v7_0_rlc_fini()
3735 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); in gfx_v7_0_rlc_fini()
3736 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_fini()
3737 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_fini()
3739 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_fini()
3740 adev->gfx.rlc.cp_table_obj = NULL; in gfx_v7_0_rlc_fini()
3744 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) in gfx_v7_0_rlc_init() argument
3753 if (adev->flags & AMD_IS_APU) { in gfx_v7_0_rlc_init()
3754 if (adev->asic_type == CHIP_KAVERI) { in gfx_v7_0_rlc_init()
3755 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3756 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3759 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3760 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3764 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3765 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4; in gfx_v7_0_rlc_init()
3767 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3768 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3771 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3775 if (adev->gfx.rlc.save_restore_obj == NULL) { in gfx_v7_0_rlc_init()
3776 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, in gfx_v7_0_rlc_init()
3780 &adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3782 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); in gfx_v7_0_rlc_init()
3787 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); in gfx_v7_0_rlc_init()
3789 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3792 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, in gfx_v7_0_rlc_init()
3793 &adev->gfx.rlc.save_restore_gpu_addr); in gfx_v7_0_rlc_init()
3795 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3796 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); in gfx_v7_0_rlc_init()
3797 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3801 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); in gfx_v7_0_rlc_init()
3803 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); in gfx_v7_0_rlc_init()
3804 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3808 dst_ptr = adev->gfx.rlc.sr_ptr; in gfx_v7_0_rlc_init()
3809 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_rlc_init()
3811 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3812 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in gfx_v7_0_rlc_init()
3817 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); in gfx_v7_0_rlc_init()
3819 if (adev->gfx.rlc.clear_state_obj == NULL) { in gfx_v7_0_rlc_init()
3820 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, in gfx_v7_0_rlc_init()
3824 &adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3826 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); in gfx_v7_0_rlc_init()
3827 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3831 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); in gfx_v7_0_rlc_init()
3833 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3836 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, in gfx_v7_0_rlc_init()
3837 &adev->gfx.rlc.clear_state_gpu_addr); in gfx_v7_0_rlc_init()
3839 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3840 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); in gfx_v7_0_rlc_init()
3841 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3845 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_rlc_init()
3847 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); in gfx_v7_0_rlc_init()
3848 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3852 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v7_0_rlc_init()
3853 gfx_v7_0_get_csb_buffer(adev, dst_ptr); in gfx_v7_0_rlc_init()
3854 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3855 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v7_0_rlc_init()
3858 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3859 if (adev->gfx.rlc.cp_table_obj == NULL) { in gfx_v7_0_rlc_init()
3860 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, in gfx_v7_0_rlc_init()
3864 &adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3866 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); in gfx_v7_0_rlc_init()
3867 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3872 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); in gfx_v7_0_rlc_init()
3874 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); in gfx_v7_0_rlc_init()
3875 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3878 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, in gfx_v7_0_rlc_init()
3879 &adev->gfx.rlc.cp_table_gpu_addr); in gfx_v7_0_rlc_init()
3881 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3882 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); in gfx_v7_0_rlc_init()
3883 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3886 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_rlc_init()
3888 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); in gfx_v7_0_rlc_init()
3889 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_rlc_init()
3893 gfx_v7_0_init_cp_pg_table(adev); in gfx_v7_0_rlc_init()
3895 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3896 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in gfx_v7_0_rlc_init()
3903 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_lbpw() argument
3915 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) in gfx_v7_0_wait_for_rlc_serdes() argument
3920 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_wait_for_rlc_serdes()
3921 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3922 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3923 gfx_v7_0_select_se_sh(adev, i, j); in gfx_v7_0_wait_for_rlc_serdes()
3924 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3931 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_wait_for_rlc_serdes()
3932 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_wait_for_rlc_serdes()
3938 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3945 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) in gfx_v7_0_update_rlc() argument
3954 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) in gfx_v7_0_halt_rlc() argument
3966 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_halt_rlc()
3972 gfx_v7_0_wait_for_rlc_serdes(adev); in gfx_v7_0_halt_rlc()
3978 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) in gfx_v7_0_enter_rlc_safe_mode() argument
3987 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_enter_rlc_safe_mode()
3993 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_enter_rlc_safe_mode()
4000 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) in gfx_v7_0_exit_rlc_safe_mode() argument
4015 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) in gfx_v7_0_rlc_stop() argument
4019 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_rlc_stop()
4021 gfx_v7_0_wait_for_rlc_serdes(adev); in gfx_v7_0_rlc_stop()
4031 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) in gfx_v7_0_rlc_start() argument
4035 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_rlc_start()
4040 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) in gfx_v7_0_rlc_reset() argument
4061 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) in gfx_v7_0_rlc_resume() argument
4068 if (!adev->gfx.rlc_fw) in gfx_v7_0_rlc_resume()
4071 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v7_0_rlc_resume()
4073 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); in gfx_v7_0_rlc_resume()
4074 adev->gfx.rlc_feature_version = le32_to_cpu( in gfx_v7_0_rlc_resume()
4077 gfx_v7_0_rlc_stop(adev); in gfx_v7_0_rlc_resume()
4083 gfx_v7_0_rlc_reset(adev); in gfx_v7_0_rlc_resume()
4085 gfx_v7_0_init_pg(adev); in gfx_v7_0_rlc_resume()
4090 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_rlc_resume()
4091 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_rlc_resume()
4095 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_rlc_resume()
4101 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gfx_v7_0_rlc_resume()
4106 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
4109 gfx_v7_0_enable_lbpw(adev, false); in gfx_v7_0_rlc_resume()
4111 if (adev->asic_type == CHIP_BONAIRE) in gfx_v7_0_rlc_resume()
4114 gfx_v7_0_rlc_start(adev); in gfx_v7_0_rlc_resume()
4119 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_cgcg() argument
4125 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) { in gfx_v7_0_enable_cgcg()
4126 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_enable_cgcg()
4128 tmp = gfx_v7_0_halt_rlc(adev); in gfx_v7_0_enable_cgcg()
4130 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_cgcg()
4131 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_enable_cgcg()
4138 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_cgcg()
4140 gfx_v7_0_update_rlc(adev, tmp); in gfx_v7_0_enable_cgcg()
4144 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_enable_cgcg()
4159 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_mgcg() argument
4163 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) { in gfx_v7_0_enable_mgcg()
4164 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) { in gfx_v7_0_enable_mgcg()
4165 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) { in gfx_v7_0_enable_mgcg()
4179 tmp = gfx_v7_0_halt_rlc(adev); in gfx_v7_0_enable_mgcg()
4181 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
4182 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_enable_mgcg()
4188 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
4190 gfx_v7_0_update_rlc(adev, tmp); in gfx_v7_0_enable_mgcg()
4192 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) { in gfx_v7_0_enable_mgcg()
4198 if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) && in gfx_v7_0_enable_mgcg()
4199 (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS)) in gfx_v7_0_enable_mgcg()
4230 tmp = gfx_v7_0_halt_rlc(adev); in gfx_v7_0_enable_mgcg()
4232 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
4233 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_enable_mgcg()
4238 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_enable_mgcg()
4240 gfx_v7_0_update_rlc(adev, tmp); in gfx_v7_0_enable_mgcg()
4244 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, in gfx_v7_0_update_cg() argument
4247 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_update_cg()
4250 gfx_v7_0_enable_mgcg(adev, true); in gfx_v7_0_update_cg()
4251 gfx_v7_0_enable_cgcg(adev, true); in gfx_v7_0_update_cg()
4253 gfx_v7_0_enable_cgcg(adev, false); in gfx_v7_0_update_cg()
4254 gfx_v7_0_enable_mgcg(adev, false); in gfx_v7_0_update_cg()
4256 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_update_cg()
4259 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, in gfx_v7_0_enable_sclk_slowdown_on_pu() argument
4265 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) in gfx_v7_0_enable_sclk_slowdown_on_pu()
4273 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, in gfx_v7_0_enable_sclk_slowdown_on_pd() argument
4279 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS)) in gfx_v7_0_enable_sclk_slowdown_on_pd()
4287 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_cp_pg() argument
4292 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP)) in gfx_v7_0_enable_cp_pg()
4300 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_enable_gds_pg() argument
4305 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS)) in gfx_v7_0_enable_gds_pg()
4313 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) in gfx_v7_0_init_cp_pg_table() argument
4321 if (adev->asic_type == CHIP_KAVERI) in gfx_v7_0_init_cp_pg_table()
4324 if (adev->gfx.rlc.cp_table_ptr == NULL) in gfx_v7_0_init_cp_pg_table()
4328 dst_ptr = adev->gfx.rlc.cp_table_ptr; in gfx_v7_0_init_cp_pg_table()
4332 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; in gfx_v7_0_init_cp_pg_table()
4334 (adev->gfx.ce_fw->data + in gfx_v7_0_init_cp_pg_table()
4340 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v7_0_init_cp_pg_table()
4342 (adev->gfx.pfp_fw->data + in gfx_v7_0_init_cp_pg_table()
4348 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v7_0_init_cp_pg_table()
4350 (adev->gfx.me_fw->data + in gfx_v7_0_init_cp_pg_table()
4356 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v7_0_init_cp_pg_table()
4358 (adev->gfx.mec_fw->data + in gfx_v7_0_init_cp_pg_table()
4364 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; in gfx_v7_0_init_cp_pg_table()
4366 (adev->gfx.mec2_fw->data + in gfx_v7_0_init_cp_pg_table()
4381 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, in gfx_v7_0_enable_gfx_cgpg() argument
4386 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) { in gfx_v7_0_enable_gfx_cgpg()
4411 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev, in gfx_v7_0_get_cu_active_bitmap() argument
4417 gfx_v7_0_select_se_sh(adev, se, sh); in gfx_v7_0_get_cu_active_bitmap()
4420 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_get_cu_active_bitmap()
4427 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { in gfx_v7_0_get_cu_active_bitmap()
4435 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) in gfx_v7_0_init_ao_cu_mask() argument
4440 gfx_v7_0_get_cu_info(adev, &cu_info); in gfx_v7_0_init_ao_cu_mask()
4452 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, in gfx_v7_0_enable_gfx_static_mgpg() argument
4458 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)) in gfx_v7_0_enable_gfx_static_mgpg()
4466 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, in gfx_v7_0_enable_gfx_dynamic_mgpg() argument
4472 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)) in gfx_v7_0_enable_gfx_dynamic_mgpg()
4483 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) in gfx_v7_0_init_gfx_cgpg() argument
4488 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
4490 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4491 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4492 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
4498 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
4500 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
4501 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
4509 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
4510 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
4532 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) in gfx_v7_0_update_gfx_pg() argument
4534 gfx_v7_0_enable_gfx_cgpg(adev, enable); in gfx_v7_0_update_gfx_pg()
4535 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); in gfx_v7_0_update_gfx_pg()
4536 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); in gfx_v7_0_update_gfx_pg()
4539 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) in gfx_v7_0_get_csb_size() argument
4545 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
4553 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
4571 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, in gfx_v7_0_get_csb_buffer() argument
4578 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
4590 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
4606 switch (adev->asic_type) { in gfx_v7_0_get_csb_buffer()
4637 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) in gfx_v7_0_init_pg() argument
4639 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | in gfx_v7_0_init_pg()
4645 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); in gfx_v7_0_init_pg()
4646 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); in gfx_v7_0_init_pg()
4647 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { in gfx_v7_0_init_pg()
4648 gfx_v7_0_init_gfx_cgpg(adev); in gfx_v7_0_init_pg()
4649 gfx_v7_0_enable_cp_pg(adev, true); in gfx_v7_0_init_pg()
4650 gfx_v7_0_enable_gds_pg(adev, true); in gfx_v7_0_init_pg()
4652 gfx_v7_0_init_ao_cu_mask(adev); in gfx_v7_0_init_pg()
4653 gfx_v7_0_update_gfx_pg(adev, true); in gfx_v7_0_init_pg()
4657 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) in gfx_v7_0_fini_pg() argument
4659 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | in gfx_v7_0_fini_pg()
4665 gfx_v7_0_update_gfx_pg(adev, false); in gfx_v7_0_fini_pg()
4666 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { in gfx_v7_0_fini_pg()
4667 gfx_v7_0_enable_cp_pg(adev, false); in gfx_v7_0_fini_pg()
4668 gfx_v7_0_enable_gds_pg(adev, false); in gfx_v7_0_fini_pg()
4681 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) in gfx_v7_0_get_gpu_clock_counter() argument
4685 mutex_lock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4689 mutex_unlock(&adev->gfx.gpu_clock_mutex); in gfx_v7_0_get_gpu_clock_counter()
4743 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_early_init() local
4745 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; in gfx_v7_0_early_init()
4746 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; in gfx_v7_0_early_init()
4747 gfx_v7_0_set_ring_funcs(adev); in gfx_v7_0_early_init()
4748 gfx_v7_0_set_irq_funcs(adev); in gfx_v7_0_early_init()
4749 gfx_v7_0_set_gds_init(adev); in gfx_v7_0_early_init()
4757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_sw_init() local
4761 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); in gfx_v7_0_sw_init()
4766 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); in gfx_v7_0_sw_init()
4771 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); in gfx_v7_0_sw_init()
4775 gfx_v7_0_scratch_init(adev); in gfx_v7_0_sw_init()
4777 r = gfx_v7_0_init_microcode(adev); in gfx_v7_0_sw_init()
4783 r = gfx_v7_0_rlc_init(adev); in gfx_v7_0_sw_init()
4790 r = gfx_v7_0_mec_init(adev); in gfx_v7_0_sw_init()
4796 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4797 ring = &adev->gfx.gfx_ring[i]; in gfx_v7_0_sw_init()
4800 r = amdgpu_ring_init(adev, ring, 1024 * 1024, in gfx_v7_0_sw_init()
4802 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, in gfx_v7_0_sw_init()
4809 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_sw_init()
4817 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_sw_init()
4827 r = amdgpu_ring_init(adev, ring, 1024 * 1024, in gfx_v7_0_sw_init()
4829 &adev->gfx.eop_irq, irq_type, in gfx_v7_0_sw_init()
4836 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, in gfx_v7_0_sw_init()
4839 NULL, NULL, &adev->gds.gds_gfx_bo); in gfx_v7_0_sw_init()
4843 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, in gfx_v7_0_sw_init()
4846 NULL, NULL, &adev->gds.gws_gfx_bo); in gfx_v7_0_sw_init()
4850 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, in gfx_v7_0_sw_init()
4853 NULL, NULL, &adev->gds.oa_gfx_bo); in gfx_v7_0_sw_init()
4863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_sw_fini() local
4865 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); in gfx_v7_0_sw_fini()
4866 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); in gfx_v7_0_sw_fini()
4867 amdgpu_bo_unref(&adev->gds.gds_gfx_bo); in gfx_v7_0_sw_fini()
4869 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4870 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v7_0_sw_fini()
4871 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4872 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v7_0_sw_fini()
4874 gfx_v7_0_cp_compute_fini(adev); in gfx_v7_0_sw_fini()
4875 gfx_v7_0_rlc_fini(adev); in gfx_v7_0_sw_fini()
4876 gfx_v7_0_mec_fini(adev); in gfx_v7_0_sw_fini()
4884 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_hw_init() local
4886 gfx_v7_0_gpu_init(adev); in gfx_v7_0_hw_init()
4889 r = gfx_v7_0_rlc_resume(adev); in gfx_v7_0_hw_init()
4893 r = gfx_v7_0_cp_resume(adev); in gfx_v7_0_hw_init()
4897 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_hw_init()
4904 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_hw_fini() local
4906 gfx_v7_0_cp_enable(adev, false); in gfx_v7_0_hw_fini()
4907 gfx_v7_0_rlc_stop(adev); in gfx_v7_0_hw_fini()
4908 gfx_v7_0_fini_pg(adev); in gfx_v7_0_hw_fini()
4915 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_suspend() local
4917 return gfx_v7_0_hw_fini(adev); in gfx_v7_0_suspend()
4922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_resume() local
4924 return gfx_v7_0_hw_init(adev); in gfx_v7_0_resume()
4929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_is_idle() local
4941 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_wait_for_idle() local
4943 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_wait_for_idle()
4957 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_print_status() local
4959 dev_info(adev->dev, "GFX 7.x registers\n"); in gfx_v7_0_print_status()
4960 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", in gfx_v7_0_print_status()
4962 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", in gfx_v7_0_print_status()
4964 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", in gfx_v7_0_print_status()
4966 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", in gfx_v7_0_print_status()
4968 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", in gfx_v7_0_print_status()
4970 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", in gfx_v7_0_print_status()
4972 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); in gfx_v7_0_print_status()
4973 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", in gfx_v7_0_print_status()
4975 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", in gfx_v7_0_print_status()
4977 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", in gfx_v7_0_print_status()
4979 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", in gfx_v7_0_print_status()
4981 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", in gfx_v7_0_print_status()
4983 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); in gfx_v7_0_print_status()
4984 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); in gfx_v7_0_print_status()
4985 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", in gfx_v7_0_print_status()
4987 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); in gfx_v7_0_print_status()
4990 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", in gfx_v7_0_print_status()
4994 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", in gfx_v7_0_print_status()
4997 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_print_status()
4998 dev_info(adev->dev, " se: %d\n", i); in gfx_v7_0_print_status()
4999 gfx_v7_0_select_se_sh(adev, i, 0xffffffff); in gfx_v7_0_print_status()
5000 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5002 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", in gfx_v7_0_print_status()
5005 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in gfx_v7_0_print_status()
5007 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5009 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5011 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", in gfx_v7_0_print_status()
5013 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5015 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5017 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5019 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5021 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5024 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", in gfx_v7_0_print_status()
5026 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", in gfx_v7_0_print_status()
5028 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", in gfx_v7_0_print_status()
5030 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5032 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5034 dev_info(adev->dev, " DB_DEBUG=0x%08X\n", in gfx_v7_0_print_status()
5036 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", in gfx_v7_0_print_status()
5038 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", in gfx_v7_0_print_status()
5040 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", in gfx_v7_0_print_status()
5042 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", in gfx_v7_0_print_status()
5044 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", in gfx_v7_0_print_status()
5046 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", in gfx_v7_0_print_status()
5048 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5050 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", in gfx_v7_0_print_status()
5052 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", in gfx_v7_0_print_status()
5054 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", in gfx_v7_0_print_status()
5056 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", in gfx_v7_0_print_status()
5058 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", in gfx_v7_0_print_status()
5060 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", in gfx_v7_0_print_status()
5063 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5065 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", in gfx_v7_0_print_status()
5067 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", in gfx_v7_0_print_status()
5069 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", in gfx_v7_0_print_status()
5072 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", in gfx_v7_0_print_status()
5074 if (adev->asic_type != CHIP_HAWAII) in gfx_v7_0_print_status()
5075 dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5078 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", in gfx_v7_0_print_status()
5080 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", in gfx_v7_0_print_status()
5082 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5084 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", in gfx_v7_0_print_status()
5086 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", in gfx_v7_0_print_status()
5088 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", in gfx_v7_0_print_status()
5090 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5092 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", in gfx_v7_0_print_status()
5094 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", in gfx_v7_0_print_status()
5096 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5098 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", in gfx_v7_0_print_status()
5101 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", in gfx_v7_0_print_status()
5103 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", in gfx_v7_0_print_status()
5107 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_print_status()
5108 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { in gfx_v7_0_print_status()
5113 dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe); in gfx_v7_0_print_status()
5114 cik_srbm_select(adev, me, pipe, 0, 0); in gfx_v7_0_print_status()
5115 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n", in gfx_v7_0_print_status()
5117 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n", in gfx_v7_0_print_status()
5119 dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n", in gfx_v7_0_print_status()
5121 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", in gfx_v7_0_print_status()
5125 cik_srbm_select(adev, me, pipe, queue, 0); in gfx_v7_0_print_status()
5126 dev_info(adev->dev, " queue: %d\n", queue); in gfx_v7_0_print_status()
5127 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5129 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", in gfx_v7_0_print_status()
5131 dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n", in gfx_v7_0_print_status()
5133 dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n", in gfx_v7_0_print_status()
5135 dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n", in gfx_v7_0_print_status()
5137 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", in gfx_v7_0_print_status()
5139 dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n", in gfx_v7_0_print_status()
5141 dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n", in gfx_v7_0_print_status()
5143 dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n", in gfx_v7_0_print_status()
5145 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n", in gfx_v7_0_print_status()
5147 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n", in gfx_v7_0_print_status()
5149 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n", in gfx_v7_0_print_status()
5151 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n", in gfx_v7_0_print_status()
5153 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", in gfx_v7_0_print_status()
5155 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", in gfx_v7_0_print_status()
5157 dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n", in gfx_v7_0_print_status()
5159 dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n", in gfx_v7_0_print_status()
5161 dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n", in gfx_v7_0_print_status()
5163 dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n", in gfx_v7_0_print_status()
5167 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_print_status()
5168 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_print_status()
5170 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", in gfx_v7_0_print_status()
5172 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5174 dev_info(adev->dev, " RLC_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5176 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", in gfx_v7_0_print_status()
5178 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", in gfx_v7_0_print_status()
5180 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", in gfx_v7_0_print_status()
5182 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", in gfx_v7_0_print_status()
5184 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", in gfx_v7_0_print_status()
5186 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5188 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5190 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", in gfx_v7_0_print_status()
5193 if (adev->asic_type == CHIP_BONAIRE) in gfx_v7_0_print_status()
5194 dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n", in gfx_v7_0_print_status()
5197 mutex_lock(&adev->srbm_mutex); in gfx_v7_0_print_status()
5199 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_print_status()
5200 dev_info(adev->dev, " VM %d:\n", i); in gfx_v7_0_print_status()
5201 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", in gfx_v7_0_print_status()
5203 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", in gfx_v7_0_print_status()
5205 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", in gfx_v7_0_print_status()
5207 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", in gfx_v7_0_print_status()
5210 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_print_status()
5211 mutex_unlock(&adev->srbm_mutex); in gfx_v7_0_print_status()
5218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_soft_reset() local
5247 gfx_v7_0_print_status((void *)adev); in gfx_v7_0_soft_reset()
5249 gfx_v7_0_fini_pg(adev); in gfx_v7_0_soft_reset()
5250 gfx_v7_0_update_cg(adev, false); in gfx_v7_0_soft_reset()
5253 gfx_v7_0_rlc_stop(adev); in gfx_v7_0_soft_reset()
5264 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
5278 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
5290 gfx_v7_0_print_status((void *)adev); in gfx_v7_0_soft_reset()
5295 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v7_0_set_gfx_eop_interrupt_state() argument
5316 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v7_0_set_compute_eop_interrupt_state() argument
5358 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, in gfx_v7_0_set_priv_reg_fault_state() argument
5383 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, in gfx_v7_0_set_priv_inst_fault_state() argument
5408 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, in gfx_v7_0_set_eop_interrupt_state() argument
5415 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); in gfx_v7_0_set_eop_interrupt_state()
5418 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v7_0_set_eop_interrupt_state()
5421 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); in gfx_v7_0_set_eop_interrupt_state()
5424 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); in gfx_v7_0_set_eop_interrupt_state()
5427 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); in gfx_v7_0_set_eop_interrupt_state()
5430 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v7_0_set_eop_interrupt_state()
5433 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); in gfx_v7_0_set_eop_interrupt_state()
5436 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); in gfx_v7_0_set_eop_interrupt_state()
5439 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); in gfx_v7_0_set_eop_interrupt_state()
5447 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, in gfx_v7_0_eop_irq() argument
5460 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
5464 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
5465 ring = &adev->gfx.compute_ring[i]; in gfx_v7_0_eop_irq()
5474 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, in gfx_v7_0_priv_reg_irq() argument
5479 schedule_work(&adev->reset_work); in gfx_v7_0_priv_reg_irq()
5483 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, in gfx_v7_0_priv_inst_irq() argument
5489 schedule_work(&adev->reset_work); in gfx_v7_0_priv_inst_irq()
5497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_set_clockgating_state() local
5502 gfx_v7_0_enable_gui_idle_interrupt(adev, false); in gfx_v7_0_set_clockgating_state()
5505 gfx_v7_0_enable_mgcg(adev, true); in gfx_v7_0_set_clockgating_state()
5506 gfx_v7_0_enable_cgcg(adev, true); in gfx_v7_0_set_clockgating_state()
5508 gfx_v7_0_enable_cgcg(adev, false); in gfx_v7_0_set_clockgating_state()
5509 gfx_v7_0_enable_mgcg(adev, false); in gfx_v7_0_set_clockgating_state()
5511 gfx_v7_0_enable_gui_idle_interrupt(adev, true); in gfx_v7_0_set_clockgating_state()
5520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in gfx_v7_0_set_powergating_state() local
5525 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG | in gfx_v7_0_set_powergating_state()
5531 gfx_v7_0_update_gfx_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5532 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) { in gfx_v7_0_set_powergating_state()
5533 gfx_v7_0_enable_cp_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5534 gfx_v7_0_enable_gds_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5590 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) in gfx_v7_0_set_ring_funcs() argument
5594 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
5595 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; in gfx_v7_0_set_ring_funcs()
5596 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5597 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; in gfx_v7_0_set_ring_funcs()
5615 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) in gfx_v7_0_set_irq_funcs() argument
5617 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v7_0_set_irq_funcs()
5618 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; in gfx_v7_0_set_irq_funcs()
5620 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5621 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; in gfx_v7_0_set_irq_funcs()
5623 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v7_0_set_irq_funcs()
5624 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; in gfx_v7_0_set_irq_funcs()
5627 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) in gfx_v7_0_set_gds_init() argument
5630 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
5631 adev->gds.gws.total_size = 64; in gfx_v7_0_set_gds_init()
5632 adev->gds.oa.total_size = 16; in gfx_v7_0_set_gds_init()
5634 if (adev->gds.mem.total_size == 64 * 1024) { in gfx_v7_0_set_gds_init()
5635 adev->gds.mem.gfx_partition_size = 4096; in gfx_v7_0_set_gds_init()
5636 adev->gds.mem.cs_partition_size = 4096; in gfx_v7_0_set_gds_init()
5638 adev->gds.gws.gfx_partition_size = 4; in gfx_v7_0_set_gds_init()
5639 adev->gds.gws.cs_partition_size = 4; in gfx_v7_0_set_gds_init()
5641 adev->gds.oa.gfx_partition_size = 4; in gfx_v7_0_set_gds_init()
5642 adev->gds.oa.cs_partition_size = 1; in gfx_v7_0_set_gds_init()
5644 adev->gds.mem.gfx_partition_size = 1024; in gfx_v7_0_set_gds_init()
5645 adev->gds.mem.cs_partition_size = 1024; in gfx_v7_0_set_gds_init()
5647 adev->gds.gws.gfx_partition_size = 16; in gfx_v7_0_set_gds_init()
5648 adev->gds.gws.cs_partition_size = 16; in gfx_v7_0_set_gds_init()
5650 adev->gds.oa.gfx_partition_size = 4; in gfx_v7_0_set_gds_init()
5651 adev->gds.oa.cs_partition_size = 4; in gfx_v7_0_set_gds_init()
5656 int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, in gfx_v7_0_get_cu_info() argument
5662 if (!adev || !cu_info) in gfx_v7_0_get_cu_info()
5665 mutex_lock(&adev->grbm_idx_mutex); in gfx_v7_0_get_cu_info()
5666 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5667 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5671 bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j); in gfx_v7_0_get_cu_info()
5674 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { in gfx_v7_0_get_cu_info()
5689 mutex_unlock(&adev->grbm_idx_mutex); in gfx_v7_0_get_cu_info()