Lines Matching refs:WREG32
1200 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); in gfx_v7_0_tiling_mode_table_init()
1293 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); in gfx_v7_0_tiling_mode_table_init()
1485 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); in gfx_v7_0_tiling_mode_table_init()
1578 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); in gfx_v7_0_tiling_mode_table_init()
1757 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); in gfx_v7_0_tiling_mode_table_init()
1850 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); in gfx_v7_0_tiling_mode_table_init()
1883 WREG32(mmGRBM_GFX_INDEX, data); in gfx_v7_0_select_se_sh()
2006 WREG32(mmPA_SC_RASTER_CONFIG, data); in gfx_v7_0_setup_rb()
2043 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in gmc_v7_0_init_compute_vmid()
2044 WREG32(mmSH_MEM_APE1_BASE, 1); in gmc_v7_0_init_compute_vmid()
2045 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gmc_v7_0_init_compute_vmid()
2046 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gmc_v7_0_init_compute_vmid()
2168 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); in gfx_v7_0_gpu_init()
2229 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); in gfx_v7_0_gpu_init()
2230 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); in gfx_v7_0_gpu_init()
2231 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); in gfx_v7_0_gpu_init()
2232 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in gfx_v7_0_gpu_init()
2233 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in gfx_v7_0_gpu_init()
2234 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); in gfx_v7_0_gpu_init()
2235 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in gfx_v7_0_gpu_init()
2236 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in gfx_v7_0_gpu_init()
2245 WREG32(mmCP_MEQ_THRESHOLDS, in gfx_v7_0_gpu_init()
2265 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); in gfx_v7_0_gpu_init()
2266 WREG32(mmSH_MEM_APE1_BASE, 1); in gfx_v7_0_gpu_init()
2267 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v7_0_gpu_init()
2268 WREG32(mmSH_MEM_BASES, 0); in gfx_v7_0_gpu_init()
2275 WREG32(mmSX_DEBUG_1, 0x20); in gfx_v7_0_gpu_init()
2277 WREG32(mmTA_CNTL_AUX, 0x00010000); in gfx_v7_0_gpu_init()
2281 WREG32(mmSPI_CONFIG_CNTL, tmp); in gfx_v7_0_gpu_init()
2283 WREG32(mmSQ_CONFIG, 1); in gfx_v7_0_gpu_init()
2285 WREG32(mmDB_DEBUG, 0); in gfx_v7_0_gpu_init()
2289 WREG32(mmDB_DEBUG2, tmp); in gfx_v7_0_gpu_init()
2293 WREG32(mmDB_DEBUG3, tmp); in gfx_v7_0_gpu_init()
2297 WREG32(mmCB_HW_CONTROL, tmp); in gfx_v7_0_gpu_init()
2299 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); in gfx_v7_0_gpu_init()
2301 WREG32(mmPA_SC_FIFO_SIZE, in gfx_v7_0_gpu_init()
2307 WREG32(mmVGT_NUM_INSTANCES, 1); in gfx_v7_0_gpu_init()
2309 WREG32(mmCP_PERFMON_CNTL, 0); in gfx_v7_0_gpu_init()
2311 WREG32(mmSQ_CONFIG, 0); in gfx_v7_0_gpu_init()
2313 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, in gfx_v7_0_gpu_init()
2317 WREG32(mmVGT_CACHE_INVALIDATION, in gfx_v7_0_gpu_init()
2321 WREG32(mmVGT_GS_VERTEX_REUSE, 16); in gfx_v7_0_gpu_init()
2322 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); in gfx_v7_0_gpu_init()
2324 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | in gfx_v7_0_gpu_init()
2326 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); in gfx_v7_0_gpu_init()
2381 WREG32(scratch, 0xCAFEDEAD); in gfx_v7_0_ring_test_ring()
2662 WREG32(scratch, 0xCAFEDEAD); in gfx_v7_0_ring_test_ib()
2745 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable()
2747 …WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_M… in gfx_v7_0_cp_gfx_enable()
2794 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2796 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_cp_gfx_load_microcode()
2797 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2804 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2806 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_cp_gfx_load_microcode()
2807 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2814 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2816 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_cp_gfx_load_microcode()
2817 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
2839 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); in gfx_v7_0_cp_gfx_start()
2840 WREG32(mmCP_ENDIAN_SWAP, 0); in gfx_v7_0_cp_gfx_start()
2841 WREG32(mmCP_DEVICE_ID, 1); in gfx_v7_0_cp_gfx_start()
2936 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v7_0_cp_gfx_resume()
2938 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in gfx_v7_0_cp_gfx_resume()
2941 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v7_0_cp_gfx_resume()
2944 WREG32(mmCP_RB_VMID, 0); in gfx_v7_0_cp_gfx_resume()
2946 WREG32(mmSCRATCH_ADDR, 0); in gfx_v7_0_cp_gfx_resume()
2956 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v7_0_cp_gfx_resume()
2959 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); in gfx_v7_0_cp_gfx_resume()
2961 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v7_0_cp_gfx_resume()
2965 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v7_0_cp_gfx_resume()
2966 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v7_0_cp_gfx_resume()
2969 WREG32(mmSCRATCH_UMSK, 0); in gfx_v7_0_cp_gfx_resume()
2972 WREG32(mmCP_RB0_CNTL, tmp); in gfx_v7_0_cp_gfx_resume()
2975 WREG32(mmCP_RB0_BASE, rb_addr); in gfx_v7_0_cp_gfx_resume()
2976 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v7_0_cp_gfx_resume()
3013 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v7_0_ring_set_wptr_gfx()
3058 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable()
3060 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
3097 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
3099 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_cp_compute_load_microcode()
3100 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
3119 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
3121 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_cp_compute_load_microcode()
3122 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
3340 WREG32(mmCP_CPF_DEBUG, tmp); in gfx_v7_0_cp_compute_resume()
3353 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); in gfx_v7_0_cp_compute_resume()
3354 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); in gfx_v7_0_cp_compute_resume()
3357 WREG32(mmCP_HPD_EOP_VMID, 0); in gfx_v7_0_cp_compute_resume()
3363 WREG32(mmCP_HPD_EOP_CONTROL, tmp); in gfx_v7_0_cp_compute_resume()
3421 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); in gfx_v7_0_cp_compute_resume()
3430 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v7_0_cp_compute_resume()
3438 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v7_0_cp_compute_resume()
3444 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); in gfx_v7_0_cp_compute_resume()
3445 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); in gfx_v7_0_cp_compute_resume()
3446 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in gfx_v7_0_cp_compute_resume()
3452 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); in gfx_v7_0_cp_compute_resume()
3453 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in gfx_v7_0_cp_compute_resume()
3457 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in gfx_v7_0_cp_compute_resume()
3463 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); in gfx_v7_0_cp_compute_resume()
3464 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in gfx_v7_0_cp_compute_resume()
3487 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in gfx_v7_0_cp_compute_resume()
3493 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); in gfx_v7_0_cp_compute_resume()
3494 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v7_0_cp_compute_resume()
3502 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v7_0_cp_compute_resume()
3504 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v7_0_cp_compute_resume()
3525 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v7_0_cp_compute_resume()
3531 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in gfx_v7_0_cp_compute_resume()
3536 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); in gfx_v7_0_cp_compute_resume()
3540 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); in gfx_v7_0_cp_compute_resume()
3588 WREG32(mmCP_INT_CNTL_RING0, tmp); in gfx_v7_0_enable_gui_idle_interrupt()
3912 WREG32(mmRLC_LB_CNTL, tmp); in gfx_v7_0_enable_lbpw()
3951 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc()
3964 WREG32(mmRLC_CNTL, data); in gfx_v7_0_halt_rlc()
3983 WREG32(mmRLC_GPR_REG2, tmp); in gfx_v7_0_enter_rlc_safe_mode()
4005 WREG32(mmRLC_GPR_REG2, tmp); in gfx_v7_0_exit_rlc_safe_mode()
4017 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
4033 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v7_0_rlc_start()
4045 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_rlc_reset()
4048 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_rlc_reset()
4081 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); in gfx_v7_0_rlc_resume()
4087 WREG32(mmRLC_LB_CNTR_INIT, 0); in gfx_v7_0_rlc_resume()
4088 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); in gfx_v7_0_rlc_resume()
4092 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v7_0_rlc_resume()
4093 WREG32(mmRLC_LB_PARAMS, 0x00600408); in gfx_v7_0_rlc_resume()
4094 WREG32(mmRLC_LB_CNTL, 0x80000004); in gfx_v7_0_rlc_resume()
4097 WREG32(mmRLC_MC_CNTL, 0); in gfx_v7_0_rlc_resume()
4098 WREG32(mmRLC_UCODE_CNTL, 0); in gfx_v7_0_rlc_resume()
4103 WREG32(mmRLC_GPM_UCODE_ADDR, 0); in gfx_v7_0_rlc_resume()
4105 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in gfx_v7_0_rlc_resume()
4106 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v7_0_rlc_resume()
4112 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); in gfx_v7_0_rlc_resume()
4132 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
4133 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
4137 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); in gfx_v7_0_enable_cgcg()
4155 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
4169 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
4177 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v7_0_enable_mgcg()
4183 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
4184 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
4187 WREG32(mmRLC_SERDES_WR_CTRL, data); in gfx_v7_0_enable_mgcg()
4205 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
4211 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v7_0_enable_mgcg()
4216 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
4222 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
4228 WREG32(mmCGTS_SM_CTRL_REG, data); in gfx_v7_0_enable_mgcg()
4234 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
4235 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
4237 WREG32(mmRLC_SERDES_WR_CTRL, data); in gfx_v7_0_enable_mgcg()
4270 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pu()
4284 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_sclk_slowdown_on_pd()
4297 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_cp_pg()
4310 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gds_pg()
4390 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
4395 WREG32(mmRLC_AUTO_PG_CTRL, data); in gfx_v7_0_enable_gfx_cgpg()
4400 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_cgpg()
4405 WREG32(mmRLC_AUTO_PG_CTRL, data); in gfx_v7_0_enable_gfx_cgpg()
4444 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp); in gfx_v7_0_init_ao_cu_mask()
4449 WREG32(mmRLC_MAX_PG_CU, tmp); in gfx_v7_0_init_ao_cu_mask()
4463 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_static_mgpg()
4477 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_enable_gfx_dynamic_mgpg()
4489 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in gfx_v7_0_init_gfx_cgpg()
4490 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4491 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
4492 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
4494 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in gfx_v7_0_init_gfx_cgpg()
4496 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); in gfx_v7_0_init_gfx_cgpg()
4499 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); in gfx_v7_0_init_gfx_cgpg()
4501 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
4507 WREG32(mmRLC_PG_CNTL, data); in gfx_v7_0_init_gfx_cgpg()
4509 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
4510 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
4515 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v7_0_init_gfx_cgpg()
4518 WREG32(mmRLC_PG_DELAY, data); in gfx_v7_0_init_gfx_cgpg()
4523 WREG32(mmRLC_PG_DELAY_2, data); in gfx_v7_0_init_gfx_cgpg()
4528 WREG32(mmRLC_AUTO_PG_CTRL, data); in gfx_v7_0_init_gfx_cgpg()
4686 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); in gfx_v7_0_get_gpu_clock_counter()
5256 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in gfx_v7_0_soft_reset()
5259 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
5265 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
5271 WREG32(mmGRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
5279 WREG32(mmSRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
5285 WREG32(mmSRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
5304 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
5309 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state()
5346 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
5351 WREG32(mec_int_cntl_reg, mec_int_cntl); in gfx_v7_0_set_compute_eop_interrupt_state()
5369 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
5374 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_reg_fault_state()
5394 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_inst_fault_state()
5399 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_priv_inst_fault_state()