Lines Matching refs:PACKET3
2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2438 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2466 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2478 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2507 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2536 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in gfx_v7_0_ring_emit_semaphore()
2542 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v7_0_ring_emit_semaphore()
2579 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_ib_gfx()
2587 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2592 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2594 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx()
2617 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_ib_compute()
2623 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_compute()
2669 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v7_0_ring_test_ib()
2852 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start()
2858 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2861 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v7_0_cp_gfx_start()
2869 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_cp_gfx_start()
2877 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
2903 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2906 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
2909 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
3634 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
3646 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3648 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3652 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_vm_flush()
3666 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_vm_flush()
3674 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
3687 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v7_0_ring_emit_vm_flush()
3691 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3693 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
4583 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_get_csb_buffer()
4586 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v7_0_get_csb_buffer()
4594 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_get_csb_buffer()
4604 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_get_csb_buffer()
4630 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_get_csb_buffer()
4633 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_get_csb_buffer()
4709 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4717 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4725 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4733 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4801 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, in gfx_v7_0_sw_init()
4828 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, in gfx_v7_0_sw_init()