39 	uint32_t val;  in fiji_set_smc_sram_address()  local
49 	val = RREG32(mmSMC_IND_ACCESS_CNTL);  in fiji_set_smc_sram_address()
50 	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);  in fiji_set_smc_sram_address()
51 	WREG32(mmSMC_IND_ACCESS_CNTL, val);  in fiji_set_smc_sram_address()
130 	uint32_t val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);  in fiji_is_smc_ram_running()  local
131 	val = REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable);  in fiji_is_smc_ram_running()
133 	return ((0 == val) && (0x20100 <= RREG32_SMC(ixSMC_PC_C)));  in fiji_is_smc_ram_running()
139 	uint32_t val;  in wait_smu_response()  local
142 		val = RREG32(mmSMC_RESP_0);  in wait_smu_response()
143 		if (REG_GET_FIELD(val, SMC_RESP_0, SMC_RESP))  in wait_smu_response()
242 	uint32_t val;
248 		val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
249 		if (REG_GET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, cken) == 0)
267 	uint32_t val;  in fiji_smu_upload_firmware_image()  local
297 	val = RREG32(mmSMC_IND_ACCESS_CNTL);  in fiji_smu_upload_firmware_image()
298 	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);  in fiji_smu_upload_firmware_image()
299 	WREG32(mmSMC_IND_ACCESS_CNTL, val);  in fiji_smu_upload_firmware_image()
306 	val = RREG32(mmSMC_IND_ACCESS_CNTL);  in fiji_smu_upload_firmware_image()
307 	val = REG_SET_FIELD(val, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);  in fiji_smu_upload_firmware_image()
308 	WREG32(mmSMC_IND_ACCESS_CNTL, val);  in fiji_smu_upload_firmware_image()
349 	uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
350 	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
351 	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
353 	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
354 	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
355 	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);
564 	uint32_t val;  in fiji_smu_start_in_protection_mode()  local
568 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_protection_mode()
569 	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);  in fiji_smu_start_in_protection_mode()
570 	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);  in fiji_smu_start_in_protection_mode()
580 	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);  in fiji_smu_start_in_protection_mode()
581 	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);  in fiji_smu_start_in_protection_mode()
582 	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);  in fiji_smu_start_in_protection_mode()
585 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_protection_mode()
586 	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);  in fiji_smu_start_in_protection_mode()
587 	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);  in fiji_smu_start_in_protection_mode()
590 	val = RREG32_SMC(ixSMU_INPUT_DATA);  in fiji_smu_start_in_protection_mode()
591 	val = REG_SET_FIELD(val, SMU_INPUT_DATA, AUTO_START, 1);  in fiji_smu_start_in_protection_mode()
592 	WREG32_SMC(ixSMU_INPUT_DATA, val);  in fiji_smu_start_in_protection_mode()
598 		val = RREG32_SMC(ixRCU_UC_EVENTS);  in fiji_smu_start_in_protection_mode()
599 		if (REG_GET_FIELD(val, RCU_UC_EVENTS, INTERRUPTS_ENABLED))  in fiji_smu_start_in_protection_mode()
616 		val = RREG32_SMC(ixSMU_STATUS);  in fiji_smu_start_in_protection_mode()
617 		if (REG_GET_FIELD(val, SMU_STATUS, SMU_DONE))  in fiji_smu_start_in_protection_mode()
628 	val = RREG32_SMC(ixSMU_STATUS);  in fiji_smu_start_in_protection_mode()
629 	if (!REG_GET_FIELD(val, SMU_STATUS, SMU_PASS)) {  in fiji_smu_start_in_protection_mode()
636 		val = RREG32_SMC(ixFIRMWARE_FLAGS);  in fiji_smu_start_in_protection_mode()
637 		if(REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))  in fiji_smu_start_in_protection_mode()
654 	uint32_t val;  in fiji_smu_start_in_non_protection_mode()  local
658 		val = RREG32_SMC(ixRCU_UC_EVENTS);  in fiji_smu_start_in_non_protection_mode()
659 		val = REG_GET_FIELD(val, RCU_UC_EVENTS, boot_seq_done);  in fiji_smu_start_in_non_protection_mode()
660 		if (val)  in fiji_smu_start_in_non_protection_mode()
674 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_non_protection_mode()
675 	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 1);  in fiji_smu_start_in_non_protection_mode()
676 	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);  in fiji_smu_start_in_non_protection_mode()
686 	val = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);  in fiji_smu_start_in_non_protection_mode()
687 	val = REG_SET_FIELD(val, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);  in fiji_smu_start_in_non_protection_mode()
688 	WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, val);  in fiji_smu_start_in_non_protection_mode()
691 	val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);  in fiji_smu_start_in_non_protection_mode()
692 	val = REG_SET_FIELD(val, SMC_SYSCON_RESET_CNTL, rst_reg, 0);  in fiji_smu_start_in_non_protection_mode()
693 	WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);  in fiji_smu_start_in_non_protection_mode()
697 		val = RREG32_SMC(ixFIRMWARE_FLAGS);  in fiji_smu_start_in_non_protection_mode()
698 		if (REG_GET_FIELD(val, FIRMWARE_FLAGS, INTERRUPTS_ENABLED))  in fiji_smu_start_in_non_protection_mode()
714 	uint32_t val;  in fiji_smu_start()  local
717 		val = RREG32_SMC(ixSMU_FIRMWARE);  in fiji_smu_start()
718 		if (!REG_GET_FIELD(val, SMU_FIRMWARE, SMU_MODE)) {  in fiji_smu_start()