37 static int fiji_set_smc_sram_address(struct amdgpu_device *adev, uint32_t smc_address, uint32_t lim…  in fiji_set_smc_sram_address()  argument
56 static int fiji_copy_bytes_to_smc(struct amdgpu_device *adev, uint32_t smc_start_address, const uin…  in fiji_copy_bytes_to_smc()  argument
72 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in fiji_copy_bytes_to_smc()
77 		result = fiji_set_smc_sram_address(adev, addr, limit);  in fiji_copy_bytes_to_smc()
93 		result = fiji_set_smc_sram_address(adev, addr, limit);  in fiji_copy_bytes_to_smc()
108 		result = fiji_set_smc_sram_address(adev, addr, limit);  in fiji_copy_bytes_to_smc()
116 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in fiji_copy_bytes_to_smc()
120 static int fiji_program_jump_on_start(struct amdgpu_device *adev)  in fiji_program_jump_on_start()  argument
123 	fiji_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);  in fiji_program_jump_on_start()
128 static bool fiji_is_smc_ram_running(struct amdgpu_device *adev)  in fiji_is_smc_ram_running()  argument
136 static int wait_smu_response(struct amdgpu_device *adev)  in wait_smu_response()  argument
141 	for (i = 0; i < adev->usec_timeout; i++) {  in wait_smu_response()
148 	if (i == adev->usec_timeout)  in wait_smu_response()
154 static int fiji_send_msg_to_smc_offset(struct amdgpu_device *adev)  in fiji_send_msg_to_smc_offset()  argument
156 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc_offset()
164 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc_offset()
172 static int fiji_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)  in fiji_send_msg_to_smc()  argument
174 	if (!fiji_is_smc_ram_running(adev))  in fiji_send_msg_to_smc()
179 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc()
186 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc()
194 static int fiji_send_msg_to_smc_without_waiting(struct amdgpu_device *adev,  in fiji_send_msg_to_smc_without_waiting()  argument
197 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc_without_waiting()
207 static int fiji_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,  in fiji_send_msg_to_smc_with_parameter()  argument
211 	if (!fiji_is_smc_ram_running(adev))  in fiji_send_msg_to_smc_with_parameter()
214 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc_with_parameter()
221 	return fiji_send_msg_to_smc(adev, msg);  in fiji_send_msg_to_smc_with_parameter()
225 					struct amdgpu_device *adev,  in fiji_send_msg_to_smc_with_parameter_without_waiting()  argument
228 	if (wait_smu_response(adev)) {  in fiji_send_msg_to_smc_with_parameter_without_waiting()
235 	return fiji_send_msg_to_smc_without_waiting(adev, msg);  in fiji_send_msg_to_smc_with_parameter_without_waiting()
239 static int fiji_wait_for_smc_inactive(struct amdgpu_device *adev)
244 	if (!fiji_is_smc_ram_running(adev))
247 	for (i = 0; i < adev->usec_timeout; i++) {
254 	if (i == adev->usec_timeout)
261 static int fiji_smu_upload_firmware_image(struct amdgpu_device *adev)  in fiji_smu_upload_firmware_image()  argument
272 	if (!adev->pm.fw)  in fiji_smu_upload_firmware_image()
275 	hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;  in fiji_smu_upload_firmware_image()
278 	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);  in fiji_smu_upload_firmware_image()
282 		(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in fiji_smu_upload_firmware_image()
294 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in fiji_smu_upload_firmware_image()
309 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in fiji_smu_upload_firmware_image()
315 static int fiji_read_smc_sram_dword(struct amdgpu_device *adev,
323 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
324 	result = fiji_set_smc_sram_address(adev, smc_address, limit);
327 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
331 static int fiji_write_smc_sram_dword(struct amdgpu_device *adev,
339 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
340 	result = fiji_set_smc_sram_address(adev, smc_address, limit);
343 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
347 static int fiji_smu_stop_smc(struct amdgpu_device *adev)
386 static int fiji_smu_populate_single_firmware_entry(struct amdgpu_device *adev,  in fiji_smu_populate_single_firmware_entry()  argument
391 	struct amdgpu_firmware_info *ucode = &adev->firmware.ucode[id];  in fiji_smu_populate_single_firmware_entry()
425 static int fiji_smu_request_load_fw(struct amdgpu_device *adev)  in fiji_smu_request_load_fw()  argument
427 	struct fiji_smu_private_data *private = (struct fiji_smu_private_data *)adev->smu.priv;  in fiji_smu_request_load_fw()
433 …fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_HI, private->smu_buffer_addr_hig…  in fiji_smu_request_load_fw()
434 …fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SMU_DRAM_ADDR_LO, private->smu_buffer_addr_low…  in fiji_smu_request_load_fw()
440 	if (!adev->firmware.smu_load)  in fiji_smu_request_load_fw()
443 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_RLC_G,  in fiji_smu_request_load_fw()
449 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_CE,  in fiji_smu_request_load_fw()
455 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_PFP,  in fiji_smu_request_load_fw()
461 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_ME,  in fiji_smu_request_load_fw()
467 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC,  in fiji_smu_request_load_fw()
473 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT1,  in fiji_smu_request_load_fw()
479 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,  in fiji_smu_request_load_fw()
485 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,  in fiji_smu_request_load_fw()
491 	if (fiji_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA1,  in fiji_smu_request_load_fw()
497 	fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_HI, private->header_addr_high);  in fiji_smu_request_load_fw()
498 	fiji_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DRV_DRAM_ADDR_LO, private->header_addr_low);  in fiji_smu_request_load_fw()
508 	if (fiji_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {  in fiji_smu_request_load_fw()
541 static int fiji_smu_check_fw_load_finish(struct amdgpu_device *adev,  in fiji_smu_check_fw_load_finish()  argument
547 	for (i = 0; i < adev->usec_timeout; i++) {  in fiji_smu_check_fw_load_finish()
553 	if (i == adev->usec_timeout) {  in fiji_smu_check_fw_load_finish()
561 static int fiji_smu_start_in_protection_mode(struct amdgpu_device *adev)  in fiji_smu_start_in_protection_mode()  argument
572 	result = fiji_smu_upload_firmware_image(adev);  in fiji_smu_start_in_protection_mode()
597 	for (i = 0; i < adev->usec_timeout; i++) {  in fiji_smu_start_in_protection_mode()
604 	if (i == adev->usec_timeout) {  in fiji_smu_start_in_protection_mode()
612 	fiji_send_msg_to_smc_offset(adev);  in fiji_smu_start_in_protection_mode()
615 	for (i = 0; i < adev->usec_timeout; i++) {  in fiji_smu_start_in_protection_mode()
622 	if (i == adev->usec_timeout) {  in fiji_smu_start_in_protection_mode()
635 	for (i = 0; i < adev->usec_timeout; i++) {  in fiji_smu_start_in_protection_mode()
642 	if (i == adev->usec_timeout) {  in fiji_smu_start_in_protection_mode()
651 static int fiji_smu_start_in_non_protection_mode(struct amdgpu_device *adev)  in fiji_smu_start_in_non_protection_mode()  argument
657 	for (i = 0; i < adev->usec_timeout; i++) {  in fiji_smu_start_in_non_protection_mode()
665 	if (i == adev->usec_timeout) {  in fiji_smu_start_in_non_protection_mode()
678 	result = fiji_smu_upload_firmware_image(adev);  in fiji_smu_start_in_non_protection_mode()
683 	fiji_program_jump_on_start(adev);  in fiji_smu_start_in_non_protection_mode()
696 	for (i = 0; i < adev->usec_timeout; i++) {  in fiji_smu_start_in_non_protection_mode()
703 	if (i == adev->usec_timeout) {  in fiji_smu_start_in_non_protection_mode()
711 int fiji_smu_start(struct amdgpu_device *adev)  in fiji_smu_start()  argument
716 	if (!fiji_is_smc_ram_running(adev)) {  in fiji_smu_start()
720 			result = fiji_smu_start_in_non_protection_mode(adev);  in fiji_smu_start()
725 			result = fiji_smu_start_in_protection_mode(adev);  in fiji_smu_start()
731 	return fiji_smu_request_load_fw(adev);  in fiji_smu_start()
740 int fiji_smu_init(struct amdgpu_device *adev)  in fiji_smu_init()  argument
745 	struct amdgpu_bo **toc_buf = &adev->smu.toc_buf;  in fiji_smu_init()
746 	struct amdgpu_bo **smu_buf = &adev->smu.smu_buf;  in fiji_smu_init()
757 	if (adev->firmware.smu_load)  in fiji_smu_init()
758 		amdgpu_ucode_init_bo(adev);  in fiji_smu_init()
760 	adev->smu.priv = private;  in fiji_smu_init()
761 	adev->smu.fw_flags = 0;  in fiji_smu_init()
764 	ret = amdgpu_bo_create(adev, image_size, PAGE_SIZE,  in fiji_smu_init()
774 	ret = amdgpu_bo_create(adev, smu_internal_buffer_size, PAGE_SIZE,  in fiji_smu_init()
784 	ret = amdgpu_bo_reserve(adev->smu.toc_buf, false);  in fiji_smu_init()
786 		amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_init()
791 	ret = amdgpu_bo_pin(adev->smu.toc_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);  in fiji_smu_init()
793 		amdgpu_bo_unreserve(adev->smu.toc_buf);  in fiji_smu_init()
794 		amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_init()
801 		amdgpu_bo_unreserve(adev->smu.toc_buf);  in fiji_smu_init()
802 		amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_init()
807 	amdgpu_bo_unreserve(adev->smu.toc_buf);  in fiji_smu_init()
812 	ret = amdgpu_bo_reserve(adev->smu.smu_buf, false);  in fiji_smu_init()
814 		amdgpu_bo_unref(&adev->smu.smu_buf);  in fiji_smu_init()
815 		amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_init()
820 	ret = amdgpu_bo_pin(adev->smu.smu_buf, AMDGPU_GEM_DOMAIN_VRAM, &mc_addr);  in fiji_smu_init()
822 		amdgpu_bo_unreserve(adev->smu.smu_buf);  in fiji_smu_init()
823 		amdgpu_bo_unref(&adev->smu.smu_buf);  in fiji_smu_init()
824 		amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_init()
831 		amdgpu_bo_unreserve(adev->smu.smu_buf);  in fiji_smu_init()
832 		amdgpu_bo_unref(&adev->smu.smu_buf);  in fiji_smu_init()
833 		amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_init()
838 	amdgpu_bo_unreserve(adev->smu.smu_buf);  in fiji_smu_init()
842 	adev->smu.smumgr_funcs = &fiji_smumgr_funcs;  in fiji_smu_init()
847 int fiji_smu_fini(struct amdgpu_device *adev)  in fiji_smu_fini()  argument
849 	amdgpu_bo_unref(&adev->smu.toc_buf);  in fiji_smu_fini()
850 	amdgpu_bo_unref(&adev->smu.smu_buf);  in fiji_smu_fini()
851 	kfree(adev->smu.priv);  in fiji_smu_fini()
852 	adev->smu.priv = NULL;  in fiji_smu_fini()
853 	if (adev->firmware.fw_buf)  in fiji_smu_fini()
854 		amdgpu_ucode_fini_bo(adev);  in fiji_smu_fini()