386 	struct drm_device *dev = adev->ddev;  in dce_v8_0_hpd_init()
441 	struct drm_device *dev = adev->ddev;  in dce_v8_0_hpd_fini()
2808 	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);  in dce_v8_0_crtc_init()
2817 	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v8_0_crtc_init()
2818 	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v8_0_crtc_init()
2897 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;  in dce_v8_0_sw_init()
2899 	adev->ddev->mode_config.max_width = 16384;  in dce_v8_0_sw_init()
2900 	adev->ddev->mode_config.max_height = 16384;  in dce_v8_0_sw_init()
2902 	adev->ddev->mode_config.preferred_depth = 24;  in dce_v8_0_sw_init()
2903 	adev->ddev->mode_config.prefer_shadow = 1;  in dce_v8_0_sw_init()
2905 	adev->ddev->mode_config.fb_base = adev->mc.aper_base;  in dce_v8_0_sw_init()
2911 	adev->ddev->mode_config.max_width = 16384;  in dce_v8_0_sw_init()
2912 	adev->ddev->mode_config.max_height = 16384;  in dce_v8_0_sw_init()
2922 		amdgpu_print_display_setup(adev->ddev);  in dce_v8_0_sw_init()
2933 	drm_kms_helper_poll_init(adev->ddev);  in dce_v8_0_sw_init()
2944 	drm_kms_helper_poll_fini(adev->ddev);  in dce_v8_0_sw_fini()
2950 	drm_mode_config_cleanup(adev->ddev);  in dce_v8_0_sw_fini()
3285 			drm_handle_vblank(adev->ddev, crtc);  in dce_v8_0_crtc_irq()
3356 	spin_lock_irqsave(&adev->ddev->event_lock, flags);  in dce_v8_0_pageflip_irq()
3363 		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);  in dce_v8_0_pageflip_irq()
3373 		drm_send_vblank_event(adev->ddev, crtc_id, works->event);  in dce_v8_0_pageflip_irq()
3375 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);  in dce_v8_0_pageflip_irq()
3377 	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);  in dce_v8_0_pageflip_irq()
3612 	struct drm_device *dev = adev->ddev;  in dce_v8_0_encoder_add()