Lines Matching refs:adev
46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, in dce_v8_0_audio_endpt_rreg() argument
122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_rreg()
130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, in dce_v8_0_audio_endpt_wreg() argument
135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_wreg()
138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v8_0_audio_endpt_wreg()
141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc) in dce_v8_0_is_in_vblank() argument
150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc) in dce_v8_0_is_counter_moving() argument
171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc) in dce_v8_0_vblank_wait() argument
175 if (crtc >= adev->mode_info.num_crtc) in dce_v8_0_vblank_wait()
184 while (dce_v8_0_is_in_vblank(adev, crtc)) { in dce_v8_0_vblank_wait()
186 if (!dce_v8_0_is_counter_moving(adev, crtc)) in dce_v8_0_vblank_wait()
191 while (!dce_v8_0_is_in_vblank(adev, crtc)) { in dce_v8_0_vblank_wait()
193 if (!dce_v8_0_is_counter_moving(adev, crtc)) in dce_v8_0_vblank_wait()
199 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) in dce_v8_0_vblank_get_counter() argument
201 if (crtc >= adev->mode_info.num_crtc) in dce_v8_0_vblank_get_counter()
207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev) in dce_v8_0_pageflip_interrupt_init() argument
212 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v8_0_pageflip_interrupt_init()
213 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v8_0_pageflip_interrupt_init()
216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) in dce_v8_0_pageflip_interrupt_fini() argument
221 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v8_0_pageflip_interrupt_fini()
222 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v8_0_pageflip_interrupt_fini()
235 static void dce_v8_0_page_flip(struct amdgpu_device *adev, in dce_v8_0_page_flip() argument
238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_page_flip()
250 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, in dce_v8_0_crtc_get_scanoutpos() argument
253 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v8_0_crtc_get_scanoutpos()
271 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, in dce_v8_0_hpd_sense() argument
316 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, in dce_v8_0_hpd_set_polarity() argument
320 bool connected = dce_v8_0_hpd_sense(adev, hpd); in dce_v8_0_hpd_set_polarity()
384 static void dce_v8_0_hpd_init(struct amdgpu_device *adev) in dce_v8_0_hpd_init() argument
386 struct drm_device *dev = adev->ddev; in dce_v8_0_hpd_init()
426 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v8_0_hpd_init()
427 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v8_0_hpd_init()
439 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) in dce_v8_0_hpd_fini() argument
441 struct drm_device *dev = adev->ddev; in dce_v8_0_hpd_fini()
469 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v8_0_hpd_fini()
473 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) in dce_v8_0_hpd_get_gpio_reg() argument
478 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) in dce_v8_0_is_display_hung() argument
484 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_is_display_hung()
492 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_is_display_hung()
507 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, in dce_v8_0_stop_mc_access() argument
522 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_stop_mc_access()
533 amdgpu_display_vblank_wait(adev, i); in dce_v8_0_stop_mc_access()
540 frame_count = amdgpu_display_vblank_get_counter(adev, i); in dce_v8_0_stop_mc_access()
541 for (j = 0; j < adev->usec_timeout; j++) { in dce_v8_0_stop_mc_access()
542 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) in dce_v8_0_stop_mc_access()
572 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, in dce_v8_0_resume_mc_access() argument
579 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_resume_mc_access()
581 upper_32_bits(adev->mc.vram_start)); in dce_v8_0_resume_mc_access()
583 upper_32_bits(adev->mc.vram_start)); in dce_v8_0_resume_mc_access()
585 (u32)adev->mc.vram_start); in dce_v8_0_resume_mc_access()
587 (u32)adev->mc.vram_start); in dce_v8_0_resume_mc_access()
605 for (j = 0; j < adev->usec_timeout; j++) { in dce_v8_0_resume_mc_access()
617 frame_count = amdgpu_display_vblank_get_counter(adev, i); in dce_v8_0_resume_mc_access()
618 for (j = 0; j < adev->usec_timeout; j++) { in dce_v8_0_resume_mc_access()
619 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) in dce_v8_0_resume_mc_access()
626 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); in dce_v8_0_resume_mc_access()
627 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); in dce_v8_0_resume_mc_access()
635 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, in dce_v8_0_set_vga_render_state() argument
660 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_program_fmt() local
744 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, in dce_v8_0_line_buffer_adjust() argument
767 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v8_0_line_buffer_adjust()
771 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v8_0_line_buffer_adjust()
784 for (i = 0; i < adev->usec_timeout; i++) { in dce_v8_0_line_buffer_adjust()
816 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) in cik_get_number_of_dram_channels() argument
1187 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, in dce_v8_0_program_watermarks() argument
1203 if (adev->pm.dpm_enabled) { in dce_v8_0_program_watermarks()
1205 amdgpu_dpm_get_mclk(adev, false) * 10; in dce_v8_0_program_watermarks()
1207 amdgpu_dpm_get_sclk(adev, false) * 10; in dce_v8_0_program_watermarks()
1209 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v8_0_program_watermarks()
1210 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()
1226 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); in dce_v8_0_program_watermarks()
1237 (adev->mode_info.disp_priority == 2)) { in dce_v8_0_program_watermarks()
1242 if (adev->pm.dpm_enabled) { in dce_v8_0_program_watermarks()
1244 amdgpu_dpm_get_mclk(adev, true) * 10; in dce_v8_0_program_watermarks()
1246 amdgpu_dpm_get_sclk(adev, true) * 10; in dce_v8_0_program_watermarks()
1248 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v8_0_program_watermarks()
1249 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()
1265 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); in dce_v8_0_program_watermarks()
1276 (adev->mode_info.disp_priority == 2)) { in dce_v8_0_program_watermarks()
1318 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev) in dce_v8_0_bandwidth_update() argument
1324 amdgpu_update_display_priority(adev); in dce_v8_0_bandwidth_update()
1326 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_bandwidth_update()
1327 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v8_0_bandwidth_update()
1330 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_bandwidth_update()
1331 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v8_0_bandwidth_update()
1332 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1333 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v8_0_bandwidth_update()
1338 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev) in dce_v8_0_audio_get_connected_pins() argument
1343 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v8_0_audio_get_connected_pins()
1344 offset = adev->mode_info.audio.pin[i].offset; in dce_v8_0_audio_get_connected_pins()
1350 adev->mode_info.audio.pin[i].connected = false; in dce_v8_0_audio_get_connected_pins()
1352 adev->mode_info.audio.pin[i].connected = true; in dce_v8_0_audio_get_connected_pins()
1356 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev) in dce_v8_0_audio_get_pin() argument
1360 dce_v8_0_audio_get_connected_pins(adev); in dce_v8_0_audio_get_pin()
1362 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v8_0_audio_get_pin()
1363 if (adev->mode_info.audio.pin[i].connected) in dce_v8_0_audio_get_pin()
1364 return &adev->mode_info.audio.pin[i]; in dce_v8_0_audio_get_pin()
1372 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v8_0_afmt_audio_select_pin() local
1389 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v8_0_audio_write_latency_fields() local
1446 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v8_0_audio_write_speaker_allocation() local
1495 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v8_0_audio_write_sad_regs() local
1579 static void dce_v8_0_audio_enable(struct amdgpu_device *adev, in dce_v8_0_audio_enable() argument
1601 static int dce_v8_0_audio_init(struct amdgpu_device *adev) in dce_v8_0_audio_init() argument
1608 adev->mode_info.audio.enabled = true; in dce_v8_0_audio_init()
1610 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */ in dce_v8_0_audio_init()
1611 adev->mode_info.audio.num_pins = 7; in dce_v8_0_audio_init()
1612 else if ((adev->asic_type == CHIP_KABINI) || in dce_v8_0_audio_init()
1613 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */ in dce_v8_0_audio_init()
1614 adev->mode_info.audio.num_pins = 3; in dce_v8_0_audio_init()
1615 else if ((adev->asic_type == CHIP_BONAIRE) || in dce_v8_0_audio_init()
1616 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */ in dce_v8_0_audio_init()
1617 adev->mode_info.audio.num_pins = 7; in dce_v8_0_audio_init()
1619 adev->mode_info.audio.num_pins = 3; in dce_v8_0_audio_init()
1621 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v8_0_audio_init()
1622 adev->mode_info.audio.pin[i].channels = -1; in dce_v8_0_audio_init()
1623 adev->mode_info.audio.pin[i].rate = -1; in dce_v8_0_audio_init()
1624 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v8_0_audio_init()
1625 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v8_0_audio_init()
1626 adev->mode_info.audio.pin[i].category_code = 0; in dce_v8_0_audio_init()
1627 adev->mode_info.audio.pin[i].connected = false; in dce_v8_0_audio_init()
1628 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v8_0_audio_init()
1629 adev->mode_info.audio.pin[i].id = i; in dce_v8_0_audio_init()
1632 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v8_0_audio_init()
1638 static void dce_v8_0_audio_fini(struct amdgpu_device *adev) in dce_v8_0_audio_fini() argument
1642 if (!adev->mode_info.audio.enabled) in dce_v8_0_audio_fini()
1645 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v8_0_audio_fini()
1646 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v8_0_audio_fini()
1648 adev->mode_info.audio.enabled = false; in dce_v8_0_audio_fini()
1657 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_afmt_update_ACR() local
1680 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_afmt_update_avi_infoframe() local
1700 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_audio_set_dto() local
1727 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_afmt_setmode() local
1752 dig->afmt->pin = dce_v8_0_audio_get_pin(adev); in dce_v8_0_afmt_setmode()
1753 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); in dce_v8_0_afmt_setmode()
1883 dce_v8_0_audio_enable(adev, dig->afmt->pin, true); in dce_v8_0_afmt_setmode()
1889 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_afmt_enable() local
1903 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); in dce_v8_0_afmt_enable()
1913 static void dce_v8_0_afmt_init(struct amdgpu_device *adev) in dce_v8_0_afmt_init() argument
1917 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v8_0_afmt_init()
1918 adev->mode_info.afmt[i] = NULL; in dce_v8_0_afmt_init()
1921 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v8_0_afmt_init()
1922 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v8_0_afmt_init()
1923 if (adev->mode_info.afmt[i]) { in dce_v8_0_afmt_init()
1924 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v8_0_afmt_init()
1925 adev->mode_info.afmt[i]->id = i; in dce_v8_0_afmt_init()
1930 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) in dce_v8_0_afmt_fini() argument
1934 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v8_0_afmt_fini()
1935 kfree(adev->mode_info.afmt[i]); in dce_v8_0_afmt_fini()
1936 adev->mode_info.afmt[i] = NULL; in dce_v8_0_afmt_fini()
1954 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_vga_enable() local
1968 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_grph_enable() local
1982 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_crtc_do_set_base() local
2195 dce_v8_0_bandwidth_update(adev); in dce_v8_0_crtc_do_set_base()
2204 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_set_interleave() local
2218 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_crtc_load_lut() local
2336 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_pick_pll() local
2341 if (adev->clock.dp_extclk) in dce_v8_0_pick_pll()
2357 if ((adev->asic_type == CHIP_KABINI) || in dce_v8_0_pick_pll()
2358 (adev->asic_type == CHIP_MULLINS)) { in dce_v8_0_pick_pll()
2384 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v8_0_lock_cursor() local
2399 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v8_0_hide_cursor() local
2409 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v8_0_show_cursor() local
2426 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v8_0_cursor_move_locked() local
2601 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_crtc_dpms() local
2613 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); in dce_v8_0_crtc_dpms()
2614 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v8_0_crtc_dpms()
2615 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v8_0_crtc_dpms()
2633 amdgpu_pm_compute_clocks(adev); in dce_v8_0_crtc_dpms()
2654 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_crtc_disable() local
2679 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_crtc_disable()
2680 if (adev->mode_info.crtcs[i] && in dce_v8_0_crtc_disable()
2681 adev->mode_info.crtcs[i]->enabled && in dce_v8_0_crtc_disable()
2683 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v8_0_crtc_disable()
2700 if ((adev->asic_type == CHIP_KAVERI) || in dce_v8_0_crtc_disable()
2701 (adev->asic_type == CHIP_BONAIRE) || in dce_v8_0_crtc_disable()
2702 (adev->asic_type == CHIP_HAWAII)) in dce_v8_0_crtc_disable()
2798 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) in dce_v8_0_crtc_init() argument
2808 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); in dce_v8_0_crtc_init()
2813 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v8_0_crtc_init()
2817 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v8_0_crtc_init()
2818 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v8_0_crtc_init()
2839 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_early_init() local
2841 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; in dce_v8_0_early_init()
2842 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; in dce_v8_0_early_init()
2844 dce_v8_0_set_display_funcs(adev); in dce_v8_0_early_init()
2845 dce_v8_0_set_irq_funcs(adev); in dce_v8_0_early_init()
2847 switch (adev->asic_type) { in dce_v8_0_early_init()
2850 adev->mode_info.num_crtc = 6; in dce_v8_0_early_init()
2851 adev->mode_info.num_hpd = 6; in dce_v8_0_early_init()
2852 adev->mode_info.num_dig = 6; in dce_v8_0_early_init()
2855 adev->mode_info.num_crtc = 4; in dce_v8_0_early_init()
2856 adev->mode_info.num_hpd = 6; in dce_v8_0_early_init()
2857 adev->mode_info.num_dig = 7; in dce_v8_0_early_init()
2861 adev->mode_info.num_crtc = 2; in dce_v8_0_early_init()
2862 adev->mode_info.num_hpd = 6; in dce_v8_0_early_init()
2863 adev->mode_info.num_dig = 6; /* ? */ in dce_v8_0_early_init()
2876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_sw_init() local
2878 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_sw_init()
2879 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); in dce_v8_0_sw_init()
2885 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); in dce_v8_0_sw_init()
2891 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); in dce_v8_0_sw_init()
2895 adev->mode_info.mode_config_initialized = true; in dce_v8_0_sw_init()
2897 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; in dce_v8_0_sw_init()
2899 adev->ddev->mode_config.max_width = 16384; in dce_v8_0_sw_init()
2900 adev->ddev->mode_config.max_height = 16384; in dce_v8_0_sw_init()
2902 adev->ddev->mode_config.preferred_depth = 24; in dce_v8_0_sw_init()
2903 adev->ddev->mode_config.prefer_shadow = 1; in dce_v8_0_sw_init()
2905 adev->ddev->mode_config.fb_base = adev->mc.aper_base; in dce_v8_0_sw_init()
2907 r = amdgpu_modeset_create_props(adev); in dce_v8_0_sw_init()
2911 adev->ddev->mode_config.max_width = 16384; in dce_v8_0_sw_init()
2912 adev->ddev->mode_config.max_height = 16384; in dce_v8_0_sw_init()
2915 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v8_0_sw_init()
2916 r = dce_v8_0_crtc_init(adev, i); in dce_v8_0_sw_init()
2921 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) in dce_v8_0_sw_init()
2922 amdgpu_print_display_setup(adev->ddev); in dce_v8_0_sw_init()
2927 dce_v8_0_afmt_init(adev); in dce_v8_0_sw_init()
2929 r = dce_v8_0_audio_init(adev); in dce_v8_0_sw_init()
2933 drm_kms_helper_poll_init(adev->ddev); in dce_v8_0_sw_init()
2940 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_sw_fini() local
2942 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v8_0_sw_fini()
2944 drm_kms_helper_poll_fini(adev->ddev); in dce_v8_0_sw_fini()
2946 dce_v8_0_audio_fini(adev); in dce_v8_0_sw_fini()
2948 dce_v8_0_afmt_fini(adev); in dce_v8_0_sw_fini()
2950 drm_mode_config_cleanup(adev->ddev); in dce_v8_0_sw_fini()
2951 adev->mode_info.mode_config_initialized = false; in dce_v8_0_sw_fini()
2959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_hw_init() local
2962 amdgpu_atombios_encoder_init_dig(adev); in dce_v8_0_hw_init()
2963 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v8_0_hw_init()
2966 dce_v8_0_hpd_init(adev); in dce_v8_0_hw_init()
2968 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v8_0_hw_init()
2969 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v8_0_hw_init()
2972 dce_v8_0_pageflip_interrupt_init(adev); in dce_v8_0_hw_init()
2980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_hw_fini() local
2982 dce_v8_0_hpd_fini(adev); in dce_v8_0_hw_fini()
2984 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v8_0_hw_fini()
2985 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v8_0_hw_fini()
2988 dce_v8_0_pageflip_interrupt_fini(adev); in dce_v8_0_hw_fini()
2995 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_suspend() local
2997 amdgpu_atombios_scratch_regs_save(adev); in dce_v8_0_suspend()
3004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_resume() local
3009 amdgpu_atombios_scratch_regs_restore(adev); in dce_v8_0_resume()
3012 if (adev->mode_info.bl_encoder) { in dce_v8_0_resume()
3013 u8 bl_level = amdgpu_display_backlight_get_level(adev, in dce_v8_0_resume()
3014 adev->mode_info.bl_encoder); in dce_v8_0_resume()
3015 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v8_0_resume()
3034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_print_status() local
3036 dev_info(adev->dev, "DCE 8.x registers\n"); in dce_v8_0_print_status()
3043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v8_0_soft_reset() local
3045 if (dce_v8_0_is_display_hung(adev)) in dce_v8_0_soft_reset()
3049 dce_v8_0_print_status((void *)adev); in dce_v8_0_soft_reset()
3053 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v8_0_soft_reset()
3065 dce_v8_0_print_status((void *)adev); in dce_v8_0_soft_reset()
3070 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, in dce_v8_0_set_crtc_vblank_interrupt_state() argument
3076 if (crtc >= adev->mode_info.num_crtc) { in dce_v8_0_set_crtc_vblank_interrupt_state()
3121 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, in dce_v8_0_set_crtc_vline_interrupt_state() argument
3127 if (crtc >= adev->mode_info.num_crtc) { in dce_v8_0_set_crtc_vline_interrupt_state()
3172 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, in dce_v8_0_set_hpd_interrupt_state() argument
3221 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev, in dce_v8_0_set_crtc_interrupt_state() argument
3228 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state); in dce_v8_0_set_crtc_interrupt_state()
3231 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state); in dce_v8_0_set_crtc_interrupt_state()
3234 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state); in dce_v8_0_set_crtc_interrupt_state()
3237 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state); in dce_v8_0_set_crtc_interrupt_state()
3240 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state); in dce_v8_0_set_crtc_interrupt_state()
3243 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state); in dce_v8_0_set_crtc_interrupt_state()
3246 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state); in dce_v8_0_set_crtc_interrupt_state()
3249 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state); in dce_v8_0_set_crtc_interrupt_state()
3252 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state); in dce_v8_0_set_crtc_interrupt_state()
3255 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state); in dce_v8_0_set_crtc_interrupt_state()
3258 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state); in dce_v8_0_set_crtc_interrupt_state()
3261 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state); in dce_v8_0_set_crtc_interrupt_state()
3269 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, in dce_v8_0_crtc_irq() argument
3275 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); in dce_v8_0_crtc_irq()
3284 if (amdgpu_irq_enabled(adev, source, irq_type)) { in dce_v8_0_crtc_irq()
3285 drm_handle_vblank(adev->ddev, crtc); in dce_v8_0_crtc_irq()
3307 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, in dce_v8_0_set_pageflip_interrupt_state() argument
3314 if (type >= adev->mode_info.num_crtc) { in dce_v8_0_set_pageflip_interrupt_state()
3330 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, in dce_v8_0_pageflip_irq() argument
3340 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_pageflip_irq()
3342 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v8_0_pageflip_irq()
3356 spin_lock_irqsave(&adev->ddev->event_lock, flags); in dce_v8_0_pageflip_irq()
3363 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); in dce_v8_0_pageflip_irq()
3373 drm_send_vblank_event(adev->ddev, crtc_id, works->event); in dce_v8_0_pageflip_irq()
3375 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); in dce_v8_0_pageflip_irq()
3377 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); in dce_v8_0_pageflip_irq()
3383 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, in dce_v8_0_hpd_irq() argument
3390 if (entry->src_data >= adev->mode_info.num_hpd) { in dce_v8_0_hpd_irq()
3404 schedule_work(&adev->hotplug_work); in dce_v8_0_hpd_irq()
3464 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v8_0_encoder_prepare() local
3476 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v8_0_encoder_prepare()
3480 amdgpu_atombios_scratch_regs_lock(adev, true); in dce_v8_0_encoder_prepare()
3504 struct amdgpu_device *adev = dev->dev_private; in dce_v8_0_encoder_commit() local
3508 amdgpu_atombios_scratch_regs_lock(adev, false); in dce_v8_0_encoder_commit()
3607 static void dce_v8_0_encoder_add(struct amdgpu_device *adev, in dce_v8_0_encoder_add() argument
3612 struct drm_device *dev = adev->ddev; in dce_v8_0_encoder_add()
3632 switch (adev->mode_info.num_crtc) { in dce_v8_0_encoder_add()
3730 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev) in dce_v8_0_set_display_funcs() argument
3732 if (adev->mode_info.funcs == NULL) in dce_v8_0_set_display_funcs()
3733 adev->mode_info.funcs = &dce_v8_0_display_funcs; in dce_v8_0_set_display_funcs()
3751 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) in dce_v8_0_set_irq_funcs() argument
3753 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; in dce_v8_0_set_irq_funcs()
3754 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; in dce_v8_0_set_irq_funcs()
3756 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; in dce_v8_0_set_irq_funcs()
3757 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; in dce_v8_0_set_irq_funcs()
3759 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; in dce_v8_0_set_irq_funcs()
3760 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; in dce_v8_0_set_irq_funcs()