Lines Matching refs:WREG32
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v8_0_audio_endpt_rreg()
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v8_0_audio_endpt_wreg()
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce_v8_0_audio_endpt_wreg()
241 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v8_0_page_flip()
244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_page_flip()
329 WREG32(mmDC_HPD1_INT_CONTROL, tmp); in dce_v8_0_hpd_set_polarity()
337 WREG32(mmDC_HPD2_INT_CONTROL, tmp); in dce_v8_0_hpd_set_polarity()
345 WREG32(mmDC_HPD3_INT_CONTROL, tmp); in dce_v8_0_hpd_set_polarity()
353 WREG32(mmDC_HPD4_INT_CONTROL, tmp); in dce_v8_0_hpd_set_polarity()
361 WREG32(mmDC_HPD5_INT_CONTROL, tmp); in dce_v8_0_hpd_set_polarity()
369 WREG32(mmDC_HPD6_INT_CONTROL, tmp); in dce_v8_0_hpd_set_polarity()
406 WREG32(mmDC_HPD1_CONTROL, tmp); in dce_v8_0_hpd_init()
409 WREG32(mmDC_HPD2_CONTROL, tmp); in dce_v8_0_hpd_init()
412 WREG32(mmDC_HPD3_CONTROL, tmp); in dce_v8_0_hpd_init()
415 WREG32(mmDC_HPD4_CONTROL, tmp); in dce_v8_0_hpd_init()
418 WREG32(mmDC_HPD5_CONTROL, tmp); in dce_v8_0_hpd_init()
421 WREG32(mmDC_HPD6_CONTROL, tmp); in dce_v8_0_hpd_init()
449 WREG32(mmDC_HPD1_CONTROL, 0); in dce_v8_0_hpd_fini()
452 WREG32(mmDC_HPD2_CONTROL, 0); in dce_v8_0_hpd_fini()
455 WREG32(mmDC_HPD3_CONTROL, 0); in dce_v8_0_hpd_fini()
458 WREG32(mmDC_HPD4_CONTROL, 0); in dce_v8_0_hpd_fini()
461 WREG32(mmDC_HPD5_CONTROL, 0); in dce_v8_0_hpd_fini()
464 WREG32(mmDC_HPD6_CONTROL, 0); in dce_v8_0_hpd_fini()
519 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v8_0_stop_mc_access()
534 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_stop_mc_access()
536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_stop_mc_access()
537 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_stop_mc_access()
549 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); in dce_v8_0_stop_mc_access()
554 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in dce_v8_0_stop_mc_access()
558 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_stop_mc_access()
561 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_stop_mc_access()
562 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_stop_mc_access()
580 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in dce_v8_0_resume_mc_access()
582 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in dce_v8_0_resume_mc_access()
584 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in dce_v8_0_resume_mc_access()
586 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], in dce_v8_0_resume_mc_access()
593 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); in dce_v8_0_resume_mc_access()
598 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); in dce_v8_0_resume_mc_access()
603 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in dce_v8_0_resume_mc_access()
613 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_resume_mc_access()
614 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_resume_mc_access()
615 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_resume_mc_access()
626 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); in dce_v8_0_resume_mc_access()
627 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); in dce_v8_0_resume_mc_access()
630 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); in dce_v8_0_resume_mc_access()
632 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); in dce_v8_0_resume_mc_access()
646 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
654 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
727 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_fmt()
778 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, in dce_v8_0_line_buffer_adjust()
782 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v8_0_line_buffer_adjust()
1287 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_watermarks()
1288 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_program_watermarks()
1295 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_program_watermarks()
1296 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_program_watermarks()
1300 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v8_0_program_watermarks()
1382 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, in dce_v8_0_afmt_audio_select_pin()
1663 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); in dce_v8_0_afmt_update_ACR()
1664 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); in dce_v8_0_afmt_update_ACR()
1666 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); in dce_v8_0_afmt_update_ACR()
1667 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); in dce_v8_0_afmt_update_ACR()
1669 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); in dce_v8_0_afmt_update_ACR()
1670 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); in dce_v8_0_afmt_update_ACR()
1687 WREG32(mmAFMT_AVI_INFO0 + offset, in dce_v8_0_afmt_update_avi_infoframe()
1689 WREG32(mmAFMT_AVI_INFO1 + offset, in dce_v8_0_afmt_update_avi_infoframe()
1691 WREG32(mmAFMT_AVI_INFO2 + offset, in dce_v8_0_afmt_update_avi_infoframe()
1693 WREG32(mmAFMT_AVI_INFO3 + offset, in dce_v8_0_afmt_update_avi_infoframe()
1715 …WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SO… in dce_v8_0_audio_set_dto()
1716 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); in dce_v8_0_audio_set_dto()
1717 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); in dce_v8_0_audio_set_dto()
1757 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
1760 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); in dce_v8_0_afmt_setmode()
1789 WREG32(mmHDMI_CONTROL + offset, val); in dce_v8_0_afmt_setmode()
1791 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
1796 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, in dce_v8_0_afmt_setmode()
1800 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, in dce_v8_0_afmt_setmode()
1803 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, in dce_v8_0_afmt_setmode()
1806 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v8_0_afmt_setmode()
1808 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
1812 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
1818 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
1821 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, in dce_v8_0_afmt_setmode()
1827 WREG32(mmAFMT_60958_0 + offset, in dce_v8_0_afmt_setmode()
1830 WREG32(mmAFMT_60958_1 + offset, in dce_v8_0_afmt_setmode()
1833 WREG32(mmAFMT_60958_2 + offset, in dce_v8_0_afmt_setmode()
1844 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, in dce_v8_0_afmt_setmode()
1877 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); in dce_v8_0_afmt_setmode()
1878 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); in dce_v8_0_afmt_setmode()
1879 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); in dce_v8_0_afmt_setmode()
1880 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); in dce_v8_0_afmt_setmode()
1959 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v8_0_vga_enable()
1961 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v8_0_vga_enable()
1971 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v8_0_grph_enable()
1973 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_grph_enable()
2128 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2130 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2132 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2134 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2136 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_crtc_do_set_base()
2137 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v8_0_crtc_do_set_base()
2151 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_do_set_base()
2152 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_do_set_base()
2153 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_do_set_base()
2154 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_do_set_base()
2155 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v8_0_crtc_do_set_base()
2156 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v8_0_crtc_do_set_base()
2159 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v8_0_crtc_do_set_base()
2163 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2168 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2172 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
2179 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v8_0_crtc_do_set_base()
2182 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); in dce_v8_0_crtc_do_set_base()
2208 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v8_0_set_interleave()
2211 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_set_interleave()
2223 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2226 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2228 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2230 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2234 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2236 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2237 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2238 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2240 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v8_0_crtc_load_lut()
2241 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v8_0_crtc_load_lut()
2242 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v8_0_crtc_load_lut()
2244 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2245 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v8_0_crtc_load_lut()
2247 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2249 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2255 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2259 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2262 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2265 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2269 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v8_0_crtc_load_lut()
2273 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_load_lut()
2393 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v8_0_lock_cursor()
2411 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v8_0_show_cursor()
2413 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_show_cursor()
2443 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v8_0_cursor_move_locked()
2444 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v8_0_cursor_move_locked()
2445 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v8_0_cursor_move_locked()
3054 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v8_0_soft_reset()
3060 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v8_0_soft_reset()
3109 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
3114 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vblank_interrupt_state()
3160 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vline_interrupt_state()
3165 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); in dce_v8_0_set_crtc_vline_interrupt_state()
3207 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); in dce_v8_0_set_hpd_interrupt_state()
3212 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); in dce_v8_0_set_hpd_interrupt_state()
3280 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); in dce_v8_0_crtc_irq()
3292 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); in dce_v8_0_crtc_irq()
3321 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v8_0_set_pageflip_interrupt_state()
3324 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v8_0_set_pageflip_interrupt_state()
3349 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], in dce_v8_0_pageflip_irq()
3403 WREG32(int_control, tmp); in dce_v8_0_hpd_irq()