Lines Matching refs:tmp
359 u32 tmp; in dce_v11_0_hpd_set_polarity() local
386 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_set_polarity()
388 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v11_0_hpd_set_polarity()
390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v11_0_hpd_set_polarity()
391 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); in dce_v11_0_hpd_set_polarity()
406 u32 tmp; in dce_v11_0_hpd_init() local
445 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_init()
446 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v11_0_hpd_init()
447 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); in dce_v11_0_hpd_init()
449 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); in dce_v11_0_hpd_init()
450 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v11_0_hpd_init()
453 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v11_0_hpd_init()
456 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); in dce_v11_0_hpd_init()
475 u32 tmp; in dce_v11_0_hpd_fini() local
504 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); in dce_v11_0_hpd_fini()
505 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v11_0_hpd_fini()
506 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); in dce_v11_0_hpd_fini()
521 u32 i, j, tmp; in dce_v11_0_is_display_hung() local
524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
525 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v11_0_is_display_hung()
534 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
535 if (tmp != crtc_status[i]) in dce_v11_0_is_display_hung()
550 u32 crtc_enabled, tmp; in dce_v11_0_stop_mc_access() local
557 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_stop_mc_access()
558 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in dce_v11_0_stop_mc_access()
559 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v11_0_stop_mc_access()
571 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
572 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { in dce_v11_0_stop_mc_access()
575 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); in dce_v11_0_stop_mc_access()
576 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_stop_mc_access()
586 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
587 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { in dce_v11_0_stop_mc_access()
588 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); in dce_v11_0_stop_mc_access()
589 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); in dce_v11_0_stop_mc_access()
591 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
592 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { in dce_v11_0_stop_mc_access()
593 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); in dce_v11_0_stop_mc_access()
594 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in dce_v11_0_stop_mc_access()
599 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
600 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); in dce_v11_0_stop_mc_access()
601 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_stop_mc_access()
615 u32 tmp, frame_count; in dce_v11_0_resume_mc_access() local
630 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
631 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { in dce_v11_0_resume_mc_access()
632 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); in dce_v11_0_resume_mc_access()
633 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); in dce_v11_0_resume_mc_access()
635 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
636 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { in dce_v11_0_resume_mc_access()
637 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); in dce_v11_0_resume_mc_access()
638 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); in dce_v11_0_resume_mc_access()
640 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
641 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { in dce_v11_0_resume_mc_access()
642 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); in dce_v11_0_resume_mc_access()
643 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in dce_v11_0_resume_mc_access()
646 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
647 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) in dce_v11_0_resume_mc_access()
651 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
652 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); in dce_v11_0_resume_mc_access()
654 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_resume_mc_access()
678 u32 tmp; in dce_v11_0_set_vga_render_state() local
681 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v11_0_set_vga_render_state()
683 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v11_0_set_vga_render_state()
685 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v11_0_set_vga_render_state()
686 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
689 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_set_vga_render_state()
691 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); in dce_v11_0_set_vga_render_state()
693 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in dce_v11_0_set_vga_render_state()
694 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
705 u32 tmp = 0; in dce_v11_0_program_fmt() local
730 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
731 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
732 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
733 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v11_0_program_fmt()
735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt()
742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
746 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); in dce_v11_0_program_fmt()
748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
749 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v11_0_program_fmt()
755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); in dce_v11_0_program_fmt()
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
762 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); in dce_v11_0_program_fmt()
770 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()
791 u32 tmp, buffer_alloc, i, mem_cfg; in dce_v11_0_line_buffer_adjust() local
821 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
822 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v11_0_line_buffer_adjust()
823 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_line_buffer_adjust()
825 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
826 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v11_0_line_buffer_adjust()
827 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v11_0_line_buffer_adjust()
830 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
831 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v11_0_line_buffer_adjust()
863 u32 tmp = RREG32(mmMC_SHARED_CHMAP); in cik_get_number_of_dram_channels() local
865 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in cik_get_number_of_dram_channels()
1095 u32 tmp, dmif_size = 12288; in dce_v11_0_latency_watermark() local
1122 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); in dce_v11_0_latency_watermark()
1130 lb_fill_bw = min(tmp, dfixed_trunc(b)); in dce_v11_0_latency_watermark()
1241 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; in dce_v11_0_program_watermarks() local
1329 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); in dce_v11_0_program_watermarks()
1330 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1331 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1332 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); in dce_v11_0_program_watermarks()
1333 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); in dce_v11_0_program_watermarks()
1334 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1336 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); in dce_v11_0_program_watermarks()
1337 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1338 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1339 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); in dce_v11_0_program_watermarks()
1340 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); in dce_v11_0_program_watermarks()
1341 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1384 u32 offset, tmp; in dce_v11_0_audio_get_connected_pins() local
1388 tmp = RREG32_AUDIO_ENDPT(offset, in dce_v11_0_audio_get_connected_pins()
1390 if (((tmp & in dce_v11_0_audio_get_connected_pins()
1418 u32 tmp; in dce_v11_0_afmt_audio_select_pin() local
1423 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1424 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()
1425 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_audio_select_pin()
1436 u32 tmp; in dce_v11_0_audio_write_latency_fields() local
1457 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v11_0_audio_write_latency_fields()
1459 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v11_0_audio_write_latency_fields()
1462 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v11_0_audio_write_latency_fields()
1464 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v11_0_audio_write_latency_fields()
1468 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); in dce_v11_0_audio_write_latency_fields()
1478 u32 tmp; in dce_v11_0_audio_write_speaker_allocation() local
1504 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1506 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v11_0_audio_write_speaker_allocation()
1509 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v11_0_audio_write_speaker_allocation()
1512 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v11_0_audio_write_speaker_allocation()
1515 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v11_0_audio_write_speaker_allocation()
1518 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); in dce_v11_0_audio_write_speaker_allocation()
1571 u32 tmp = 0; in dce_v11_0_audio_write_sad_regs() local
1581 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v11_0_audio_write_sad_regs()
1583 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v11_0_audio_write_sad_regs()
1585 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v11_0_audio_write_sad_regs()
1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v11_0_audio_write_sad_regs()
1599 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v11_0_audio_write_sad_regs()
1678 u32 tmp; in dce_v11_0_afmt_update_ACR() local
1680 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v11_0_afmt_update_ACR()
1682 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1683 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v11_0_afmt_update_ACR()
1685 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1687 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v11_0_afmt_update_ACR()
1689 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1690 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1691 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v11_0_afmt_update_ACR()
1692 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1694 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1695 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v11_0_afmt_update_ACR()
1696 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1697 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1698 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v11_0_afmt_update_ACR()
1699 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1735 u32 tmp; in dce_v11_0_audio_set_dto() local
1745 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); in dce_v11_0_audio_set_dto()
1746 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, in dce_v11_0_audio_set_dto()
1748 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); in dce_v11_0_audio_set_dto()
1767 u32 tmp; in dce_v11_0_afmt_setmode() local
1789 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1790 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); in dce_v11_0_afmt_setmode()
1791 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v11_0_afmt_setmode()
1795 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1802 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v11_0_afmt_setmode()
1803 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v11_0_afmt_setmode()
1808 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v11_0_afmt_setmode()
1809 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v11_0_afmt_setmode()
1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v11_0_afmt_setmode()
1815 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v11_0_afmt_setmode()
1820 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1822 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1823 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when re… in dce_v11_0_afmt_setmode()
1824 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packet… in dce_v11_0_afmt_setmode()
1825 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packet… in dce_v11_0_afmt_setmode()
1826 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1828 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1830 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce_v11_0_afmt_setmode()
1832 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); in dce_v11_0_afmt_setmode()
1833 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1835 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1837 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in dce_v11_0_afmt_setmode()
1838 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1842 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); in dce_v11_0_afmt_setmode()
1843 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1847 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1849 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); in dce_v11_0_afmt_setmode()
1851 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); in dce_v11_0_afmt_setmode()
1852 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1854 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1856 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in dce_v11_0_afmt_setmode()
1857 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1859 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1862 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v11_0_afmt_setmode()
1865 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v11_0_afmt_setmode()
1867 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v11_0_afmt_setmode()
1868 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1872 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1873 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); in dce_v11_0_afmt_setmode()
1874 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1876 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1877 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in dce_v11_0_afmt_setmode()
1878 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1880 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1881 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); in dce_v11_0_afmt_setmode()
1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); in dce_v11_0_afmt_setmode()
1883 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); in dce_v11_0_afmt_setmode()
1884 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); in dce_v11_0_afmt_setmode()
1885 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); in dce_v11_0_afmt_setmode()
1886 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); in dce_v11_0_afmt_setmode()
1887 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1912 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1914 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); in dce_v11_0_afmt_setmode()
1916 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); in dce_v11_0_afmt_setmode()
1917 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1919 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1920 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); in dce_v11_0_afmt_setmode()
1921 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1923 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1925 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); in dce_v11_0_afmt_setmode()
1926 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
2042 u32 tmp, viewport_w, viewport_h; in dce_v11_0_crtc_do_set_base() local
2208 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2210 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); in dce_v11_0_crtc_do_set_base()
2212 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); in dce_v11_0_crtc_do_set_base()
2213 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2244 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2245 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v11_0_crtc_do_set_base()
2247 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2274 u32 tmp; in dce_v11_0_set_interleave() local
2276 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2278 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); in dce_v11_0_set_interleave()
2280 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); in dce_v11_0_set_interleave()
2281 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_set_interleave()
2290 u32 tmp; in dce_v11_0_crtc_load_lut() local
2294 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2295 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); in dce_v11_0_crtc_load_lut()
2296 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2298 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2299 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_v11_0_crtc_load_lut()
2300 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2302 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2303 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); in dce_v11_0_crtc_load_lut()
2304 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2327 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2328 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); in dce_v11_0_crtc_load_lut()
2329 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); in dce_v11_0_crtc_load_lut()
2330 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); in dce_v11_0_crtc_load_lut()
2331 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2333 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2334 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); in dce_v11_0_crtc_load_lut()
2335 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2337 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2338 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); in dce_v11_0_crtc_load_lut()
2339 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2341 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2342 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); in dce_v11_0_crtc_load_lut()
2343 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2350 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2351 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); in dce_v11_0_crtc_load_lut()
2352 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2475 u32 tmp; in dce_v11_0_hide_cursor() local
2477 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_hide_cursor()
2478 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); in dce_v11_0_hide_cursor()
2479 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2486 u32 tmp; in dce_v11_0_show_cursor() local
2493 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_show_cursor()
2494 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); in dce_v11_0_show_cursor()
2495 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); in dce_v11_0_show_cursor()
2496 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
3127 u32 srbm_soft_reset = 0, tmp; in dce_v11_0_soft_reset() local
3136 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3137 tmp |= srbm_soft_reset; in dce_v11_0_soft_reset()
3138 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v11_0_soft_reset()
3139 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v11_0_soft_reset()
3140 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3144 tmp &= ~srbm_soft_reset; in dce_v11_0_soft_reset()
3145 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v11_0_soft_reset()
3146 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3218 u32 tmp; in dce_v11_0_set_hpd_irq_state() local
3227 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3228 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v11_0_set_hpd_irq_state()
3229 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3232 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3233 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); in dce_v11_0_set_hpd_irq_state()
3234 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3370 u32 tmp; in dce_v11_0_hpd_int_ack() local
3377 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3378 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); in dce_v11_0_hpd_int_ack()
3379 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
3385 u32 tmp; in dce_v11_0_crtc_vblank_int_ack() local
3392 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); in dce_v11_0_crtc_vblank_int_ack()
3393 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); in dce_v11_0_crtc_vblank_int_ack()
3394 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v11_0_crtc_vblank_int_ack()
3400 u32 tmp; in dce_v11_0_crtc_vline_int_ack() local
3407 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v11_0_crtc_vline_int_ack()
3408 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v11_0_crtc_vline_int_ack()
3409 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); in dce_v11_0_crtc_vline_int_ack()