1420 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_afmt_audio_select_pin()
1423 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_audio_select_pin()
1424 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);  in dce_v11_0_afmt_audio_select_pin()
1425 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_audio_select_pin()
1439 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_latency_fields()
1467 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_latency_fields()
1482 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_speaker_allocation()
1504 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_speaker_allocation()
1517 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,  in dce_v11_0_audio_write_speaker_allocation()
1548 	if (!dig || !dig->afmt || !dig->afmt->pin)  in dce_v11_0_audio_write_sad_regs()
1599 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);  in dce_v11_0_audio_write_sad_regs()
1680 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1682 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1683 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1685 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1687 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1689 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1690 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1692 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1694 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1696 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1697 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);  in dce_v11_0_afmt_update_ACR()
1699 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_update_ACR()
1716 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1718 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1720 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1722 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,  in dce_v11_0_afmt_update_avi_infoframe()
1737 	if (!dig || !dig->afmt)  in dce_v11_0_audio_set_dto()
1770 	if (!dig || !dig->afmt)  in dce_v11_0_afmt_setmode()
1774 	if (!dig->afmt->enabled)  in dce_v11_0_afmt_setmode()
1784 	dig->afmt->pin = dce_v11_0_audio_get_pin(adev);  in dce_v11_0_afmt_setmode()
1785 	dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_setmode()
1789 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1791 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */  in dce_v11_0_afmt_setmode()
1793 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);  in dce_v11_0_afmt_setmode()
1795 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1820 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1822 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1826 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1828 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1833 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1835 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1838 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1840 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1843 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1845 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */  in dce_v11_0_afmt_setmode()
1847 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1852 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1854 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1857 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1859 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1868 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1872 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1874 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1876 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1878 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1880 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1887 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1891 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,  in dce_v11_0_afmt_setmode()
1912 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1917 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1919 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1921 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1923 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);  in dce_v11_0_afmt_setmode()
1926 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);  in dce_v11_0_afmt_setmode()
1928 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);  in dce_v11_0_afmt_setmode()
1929 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);  in dce_v11_0_afmt_setmode()
1930 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);  in dce_v11_0_afmt_setmode()
1931 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);  in dce_v11_0_afmt_setmode()
1934 	dce_v11_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v11_0_afmt_setmode()
1944 	if (!dig || !dig->afmt)  in dce_v11_0_afmt_enable()
1948 	if (enable && dig->afmt->enabled)  in dce_v11_0_afmt_enable()
1950 	if (!enable && !dig->afmt->enabled)  in dce_v11_0_afmt_enable()
1953 	if (!enable && dig->afmt->pin) {  in dce_v11_0_afmt_enable()
1954 		dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_enable()
1955 		dig->afmt->pin = NULL;  in dce_v11_0_afmt_enable()
1958 	dig->afmt->enabled = enable;  in dce_v11_0_afmt_enable()
1961 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);  in dce_v11_0_afmt_enable()
1969 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_init()
1973 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v11_0_afmt_init()
1974 		if (adev->mode_info.afmt[i]) {  in dce_v11_0_afmt_init()
1975 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v11_0_afmt_init()
1976 			adev->mode_info.afmt[i]->id = i;  in dce_v11_0_afmt_init()
1986 		kfree(adev->mode_info.afmt[i]);  in dce_v11_0_afmt_fini()
1987 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_fini()
3539 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v11_0_encoder_prepare()