43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)  in dce_v11_0_init_golden_registers()  argument
138 	switch (adev->asic_type) {  in dce_v11_0_init_golden_registers()
140 		amdgpu_program_register_sequence(adev,  in dce_v11_0_init_golden_registers()
143 		amdgpu_program_register_sequence(adev,  in dce_v11_0_init_golden_registers()
148 		amdgpu_program_register_sequence(adev,  in dce_v11_0_init_golden_registers()
157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,  in dce_v11_0_audio_endpt_rreg()  argument
163 	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);  in dce_v11_0_audio_endpt_rreg()
166 	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);  in dce_v11_0_audio_endpt_rreg()
171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,  in dce_v11_0_audio_endpt_wreg()  argument
176 	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);  in dce_v11_0_audio_endpt_wreg()
179 	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);  in dce_v11_0_audio_endpt_wreg()
182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)  in dce_v11_0_is_in_vblank()  argument
191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)  in dce_v11_0_is_counter_moving()  argument
212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)  in dce_v11_0_vblank_wait()  argument
216 	if (crtc >= adev->mode_info.num_crtc)  in dce_v11_0_vblank_wait()
225 	while (dce_v11_0_is_in_vblank(adev, crtc)) {  in dce_v11_0_vblank_wait()
227 			if (!dce_v11_0_is_counter_moving(adev, crtc))  in dce_v11_0_vblank_wait()
232 	while (!dce_v11_0_is_in_vblank(adev, crtc)) {  in dce_v11_0_vblank_wait()
234 			if (!dce_v11_0_is_counter_moving(adev, crtc))  in dce_v11_0_vblank_wait()
240 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)  in dce_v11_0_vblank_get_counter()  argument
242 	if (crtc >= adev->mode_info.num_crtc)  in dce_v11_0_vblank_get_counter()
248 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)  in dce_v11_0_pageflip_interrupt_init()  argument
253 	for (i = 0; i < adev->mode_info.num_crtc; i++)  in dce_v11_0_pageflip_interrupt_init()
254 		amdgpu_irq_get(adev, &adev->pageflip_irq, i);  in dce_v11_0_pageflip_interrupt_init()
257 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)  in dce_v11_0_pageflip_interrupt_fini()  argument
262 	for (i = 0; i < adev->mode_info.num_crtc; i++)  in dce_v11_0_pageflip_interrupt_fini()
263 		amdgpu_irq_put(adev, &adev->pageflip_irq, i);  in dce_v11_0_pageflip_interrupt_fini()
276 static void dce_v11_0_page_flip(struct amdgpu_device *adev,  in dce_v11_0_page_flip()  argument
279 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v11_0_page_flip()
291 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,  in dce_v11_0_crtc_get_scanoutpos()  argument
294 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))  in dce_v11_0_crtc_get_scanoutpos()
312 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,  in dce_v11_0_hpd_sense()  argument
356 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,  in dce_v11_0_hpd_set_polarity()  argument
360 	bool connected = dce_v11_0_hpd_sense(adev, hpd);  in dce_v11_0_hpd_set_polarity()
402 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)  in dce_v11_0_hpd_init()  argument
404 	struct drm_device *dev = adev->ddev;  in dce_v11_0_hpd_init()
458 		dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
459 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_init()
471 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)  in dce_v11_0_hpd_fini()  argument
473 	struct drm_device *dev = adev->ddev;  in dce_v11_0_hpd_fini()
508 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v11_0_hpd_fini()
512 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)  in dce_v11_0_hpd_get_gpio_reg()  argument
517 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)  in dce_v11_0_is_display_hung()  argument
523 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_is_display_hung()
532 		for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_is_display_hung()
547 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,  in dce_v11_0_stop_mc_access()  argument
562 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_stop_mc_access()
573 				amdgpu_display_vblank_wait(adev, i);  in dce_v11_0_stop_mc_access()
580 			frame_count = amdgpu_display_vblank_get_counter(adev, i);  in dce_v11_0_stop_mc_access()
581 			for (j = 0; j < adev->usec_timeout; j++) {  in dce_v11_0_stop_mc_access()
582 				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)  in dce_v11_0_stop_mc_access()
612 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,  in dce_v11_0_resume_mc_access()  argument
619 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_resume_mc_access()
621 		       upper_32_bits(adev->mc.vram_start));  in dce_v11_0_resume_mc_access()
623 		       upper_32_bits(adev->mc.vram_start));  in dce_v11_0_resume_mc_access()
625 		       (u32)adev->mc.vram_start);  in dce_v11_0_resume_mc_access()
627 		       (u32)adev->mc.vram_start);  in dce_v11_0_resume_mc_access()
645 			for (j = 0; j < adev->usec_timeout; j++) {  in dce_v11_0_resume_mc_access()
657 			frame_count = amdgpu_display_vblank_get_counter(adev, i);  in dce_v11_0_resume_mc_access()
658 			for (j = 0; j < adev->usec_timeout; j++) {  in dce_v11_0_resume_mc_access()
659 				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)  in dce_v11_0_resume_mc_access()
666 	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));  in dce_v11_0_resume_mc_access()
667 	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));  in dce_v11_0_resume_mc_access()
675 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,  in dce_v11_0_set_vga_render_state()  argument
700 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_program_fmt()  local
787 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,  in dce_v11_0_line_buffer_adjust()  argument
810 			buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;  in dce_v11_0_line_buffer_adjust()
814 			buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;  in dce_v11_0_line_buffer_adjust()
829 	for (i = 0; i < adev->usec_timeout; i++) {  in dce_v11_0_line_buffer_adjust()
861 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)  in cik_get_number_of_dram_channels()  argument
1232 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,  in dce_v11_0_program_watermarks()  argument
1248 		if (adev->pm.dpm_enabled) {  in dce_v11_0_program_watermarks()
1250 				amdgpu_dpm_get_mclk(adev, false) * 10;  in dce_v11_0_program_watermarks()
1252 				amdgpu_dpm_get_sclk(adev, false) * 10;  in dce_v11_0_program_watermarks()
1254 			wm_high.yclk = adev->pm.current_mclk * 10;  in dce_v11_0_program_watermarks()
1255 			wm_high.sclk = adev->pm.current_sclk * 10;  in dce_v11_0_program_watermarks()
1271 		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);  in dce_v11_0_program_watermarks()
1282 		    (adev->mode_info.disp_priority == 2)) {  in dce_v11_0_program_watermarks()
1287 		if (adev->pm.dpm_enabled) {  in dce_v11_0_program_watermarks()
1289 				amdgpu_dpm_get_mclk(adev, true) * 10;  in dce_v11_0_program_watermarks()
1291 				amdgpu_dpm_get_sclk(adev, true) * 10;  in dce_v11_0_program_watermarks()
1293 			wm_low.yclk = adev->pm.current_mclk * 10;  in dce_v11_0_program_watermarks()
1294 			wm_low.sclk = adev->pm.current_sclk * 10;  in dce_v11_0_program_watermarks()
1310 		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);  in dce_v11_0_program_watermarks()
1321 		    (adev->mode_info.disp_priority == 2)) {  in dce_v11_0_program_watermarks()
1361 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)  in dce_v11_0_bandwidth_update()  argument
1367 	amdgpu_update_display_priority(adev);  in dce_v11_0_bandwidth_update()
1369 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_bandwidth_update()
1370 		if (adev->mode_info.crtcs[i]->base.enabled)  in dce_v11_0_bandwidth_update()
1373 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_bandwidth_update()
1374 		mode = &adev->mode_info.crtcs[i]->base.mode;  in dce_v11_0_bandwidth_update()
1375 		lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);  in dce_v11_0_bandwidth_update()
1376 		dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],  in dce_v11_0_bandwidth_update()
1381 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)  in dce_v11_0_audio_get_connected_pins()  argument
1386 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {  in dce_v11_0_audio_get_connected_pins()
1387 		offset = adev->mode_info.audio.pin[i].offset;  in dce_v11_0_audio_get_connected_pins()
1393 			adev->mode_info.audio.pin[i].connected = false;  in dce_v11_0_audio_get_connected_pins()
1395 			adev->mode_info.audio.pin[i].connected = true;  in dce_v11_0_audio_get_connected_pins()
1399 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)  in dce_v11_0_audio_get_pin()  argument
1403 	dce_v11_0_audio_get_connected_pins(adev);  in dce_v11_0_audio_get_pin()
1405 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {  in dce_v11_0_audio_get_pin()
1406 		if (adev->mode_info.audio.pin[i].connected)  in dce_v11_0_audio_get_pin()
1407 			return &adev->mode_info.audio.pin[i];  in dce_v11_0_audio_get_pin()
1415 	struct amdgpu_device *adev = encoder->dev->dev_private;  in dce_v11_0_afmt_audio_select_pin()  local
1431 	struct amdgpu_device *adev = encoder->dev->dev_private;  in dce_v11_0_audio_write_latency_fields()  local
1473 	struct amdgpu_device *adev = encoder->dev->dev_private;  in dce_v11_0_audio_write_speaker_allocation()  local
1525 	struct amdgpu_device *adev = encoder->dev->dev_private;  in dce_v11_0_audio_write_sad_regs()  local
1605 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,  in dce_v11_0_audio_enable()  argument
1627 static int dce_v11_0_audio_init(struct amdgpu_device *adev)  in dce_v11_0_audio_init()  argument
1634 	adev->mode_info.audio.enabled = true;  in dce_v11_0_audio_init()
1636 	adev->mode_info.audio.num_pins = 7;  in dce_v11_0_audio_init()
1638 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {  in dce_v11_0_audio_init()
1639 		adev->mode_info.audio.pin[i].channels = -1;  in dce_v11_0_audio_init()
1640 		adev->mode_info.audio.pin[i].rate = -1;  in dce_v11_0_audio_init()
1641 		adev->mode_info.audio.pin[i].bits_per_sample = -1;  in dce_v11_0_audio_init()
1642 		adev->mode_info.audio.pin[i].status_bits = 0;  in dce_v11_0_audio_init()
1643 		adev->mode_info.audio.pin[i].category_code = 0;  in dce_v11_0_audio_init()
1644 		adev->mode_info.audio.pin[i].connected = false;  in dce_v11_0_audio_init()
1645 		adev->mode_info.audio.pin[i].offset = pin_offsets[i];  in dce_v11_0_audio_init()
1646 		adev->mode_info.audio.pin[i].id = i;  in dce_v11_0_audio_init()
1649 		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);  in dce_v11_0_audio_init()
1655 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)  in dce_v11_0_audio_fini()  argument
1659 	if (!adev->mode_info.audio.enabled)  in dce_v11_0_audio_fini()
1662 	for (i = 0; i < adev->mode_info.audio.num_pins; i++)  in dce_v11_0_audio_fini()
1663 		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);  in dce_v11_0_audio_fini()
1665 	adev->mode_info.audio.enabled = false;  in dce_v11_0_audio_fini()
1674 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_afmt_update_ACR()  local
1710 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_afmt_update_avi_infoframe()  local
1729 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_audio_set_dto()  local
1760 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_afmt_setmode()  local
1784 	dig->afmt->pin = dce_v11_0_audio_get_pin(adev);  in dce_v11_0_afmt_setmode()
1785 	dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_setmode()
1934 	dce_v11_0_audio_enable(adev, dig->afmt->pin, true);  in dce_v11_0_afmt_setmode()
1940 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_afmt_enable()  local
1954 		dce_v11_0_audio_enable(adev, dig->afmt->pin, false);  in dce_v11_0_afmt_enable()
1964 static void dce_v11_0_afmt_init(struct amdgpu_device *adev)  in dce_v11_0_afmt_init()  argument
1968 	for (i = 0; i < adev->mode_info.num_dig; i++)  in dce_v11_0_afmt_init()
1969 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_init()
1972 	for (i = 0; i < adev->mode_info.num_dig; i++) {  in dce_v11_0_afmt_init()
1973 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);  in dce_v11_0_afmt_init()
1974 		if (adev->mode_info.afmt[i]) {  in dce_v11_0_afmt_init()
1975 			adev->mode_info.afmt[i]->offset = dig_offsets[i];  in dce_v11_0_afmt_init()
1976 			adev->mode_info.afmt[i]->id = i;  in dce_v11_0_afmt_init()
1981 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)  in dce_v11_0_afmt_fini()  argument
1985 	for (i = 0; i < adev->mode_info.num_dig; i++) {  in dce_v11_0_afmt_fini()
1986 		kfree(adev->mode_info.afmt[i]);  in dce_v11_0_afmt_fini()
1987 		adev->mode_info.afmt[i] = NULL;  in dce_v11_0_afmt_fini()
2005 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_vga_enable()  local
2019 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_grph_enable()  local
2033 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_crtc_do_set_base()  local
2263 	dce_v11_0_bandwidth_update(adev);  in dce_v11_0_crtc_do_set_base()
2272 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_set_interleave()  local
2288 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_crtc_load_lut()  local
2414 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_pick_pll()  local
2419 		if (adev->clock.dp_extclk)  in dce_v11_0_pick_pll()
2437 	if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {  in dce_v11_0_pick_pll()
2459 	struct amdgpu_device *adev = crtc->dev->dev_private;  in dce_v11_0_lock_cursor()  local
2474 	struct amdgpu_device *adev = crtc->dev->dev_private;  in dce_v11_0_hide_cursor()  local
2485 	struct amdgpu_device *adev = crtc->dev->dev_private;  in dce_v11_0_show_cursor()  local
2503 	struct amdgpu_device *adev = crtc->dev->dev_private;  in dce_v11_0_cursor_move_locked()  local
2678 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_crtc_dpms()  local
2690 		type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);  in dce_v11_0_crtc_dpms()
2691 		amdgpu_irq_update(adev, &adev->crtc_irq, type);  in dce_v11_0_crtc_dpms()
2692 		amdgpu_irq_update(adev, &adev->pageflip_irq, type);  in dce_v11_0_crtc_dpms()
2710 	amdgpu_pm_compute_clocks(adev);  in dce_v11_0_crtc_dpms()
2731 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_crtc_disable()  local
2756 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_crtc_disable()
2757 		if (adev->mode_info.crtcs[i] &&  in dce_v11_0_crtc_disable()
2758 		    adev->mode_info.crtcs[i]->enabled &&  in dce_v11_0_crtc_disable()
2760 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {  in dce_v11_0_crtc_disable()
2868 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)  in dce_v11_0_crtc_init()  argument
2878 	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);  in dce_v11_0_crtc_init()
2883 	adev->mode_info.crtcs[index] = amdgpu_crtc;  in dce_v11_0_crtc_init()
2887 	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v11_0_crtc_init()
2888 	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v11_0_crtc_init()
2929 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_early_init()  local
2931 	adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;  in dce_v11_0_early_init()
2932 	adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;  in dce_v11_0_early_init()
2934 	dce_v11_0_set_display_funcs(adev);  in dce_v11_0_early_init()
2935 	dce_v11_0_set_irq_funcs(adev);  in dce_v11_0_early_init()
2937 	switch (adev->asic_type) {  in dce_v11_0_early_init()
2939 		adev->mode_info.num_crtc = 3;  in dce_v11_0_early_init()
2940 		adev->mode_info.num_hpd = 6;  in dce_v11_0_early_init()
2941 		adev->mode_info.num_dig = 9;  in dce_v11_0_early_init()
2944 		adev->mode_info.num_crtc = 2;  in dce_v11_0_early_init()
2945 		adev->mode_info.num_hpd = 6;  in dce_v11_0_early_init()
2946 		adev->mode_info.num_dig = 9;  in dce_v11_0_early_init()
2959 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_sw_init()  local
2961 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_sw_init()
2962 		r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);  in dce_v11_0_sw_init()
2968 		r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);  in dce_v11_0_sw_init()
2974 	r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);  in dce_v11_0_sw_init()
2978 	adev->mode_info.mode_config_initialized = true;  in dce_v11_0_sw_init()
2980 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;  in dce_v11_0_sw_init()
2982 	adev->ddev->mode_config.max_width = 16384;  in dce_v11_0_sw_init()
2983 	adev->ddev->mode_config.max_height = 16384;  in dce_v11_0_sw_init()
2985 	adev->ddev->mode_config.preferred_depth = 24;  in dce_v11_0_sw_init()
2986 	adev->ddev->mode_config.prefer_shadow = 1;  in dce_v11_0_sw_init()
2988 	adev->ddev->mode_config.fb_base = adev->mc.aper_base;  in dce_v11_0_sw_init()
2990 	r = amdgpu_modeset_create_props(adev);  in dce_v11_0_sw_init()
2994 	adev->ddev->mode_config.max_width = 16384;  in dce_v11_0_sw_init()
2995 	adev->ddev->mode_config.max_height = 16384;  in dce_v11_0_sw_init()
2998 	for (i = 0; i < adev->mode_info.num_crtc; i++) {  in dce_v11_0_sw_init()
2999 		r = dce_v11_0_crtc_init(adev, i);  in dce_v11_0_sw_init()
3004 	if (amdgpu_atombios_get_connector_info_from_object_table(adev))  in dce_v11_0_sw_init()
3005 		amdgpu_print_display_setup(adev->ddev);  in dce_v11_0_sw_init()
3010 	dce_v11_0_afmt_init(adev);  in dce_v11_0_sw_init()
3012 	r = dce_v11_0_audio_init(adev);  in dce_v11_0_sw_init()
3016 	drm_kms_helper_poll_init(adev->ddev);  in dce_v11_0_sw_init()
3023 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_sw_fini()  local
3025 	kfree(adev->mode_info.bios_hardcoded_edid);  in dce_v11_0_sw_fini()
3027 	drm_kms_helper_poll_fini(adev->ddev);  in dce_v11_0_sw_fini()
3029 	dce_v11_0_audio_fini(adev);  in dce_v11_0_sw_fini()
3031 	dce_v11_0_afmt_fini(adev);  in dce_v11_0_sw_fini()
3033 	adev->mode_info.mode_config_initialized = false;  in dce_v11_0_sw_fini()
3041 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_hw_init()  local
3043 	dce_v11_0_init_golden_registers(adev);  in dce_v11_0_hw_init()
3046 	amdgpu_atombios_crtc_powergate_init(adev);  in dce_v11_0_hw_init()
3047 	amdgpu_atombios_encoder_init_dig(adev);  in dce_v11_0_hw_init()
3048 	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);  in dce_v11_0_hw_init()
3051 	dce_v11_0_hpd_init(adev);  in dce_v11_0_hw_init()
3053 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {  in dce_v11_0_hw_init()
3054 		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);  in dce_v11_0_hw_init()
3057 	dce_v11_0_pageflip_interrupt_init(adev);  in dce_v11_0_hw_init()
3065 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_hw_fini()  local
3067 	dce_v11_0_hpd_fini(adev);  in dce_v11_0_hw_fini()
3069 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {  in dce_v11_0_hw_fini()
3070 		dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);  in dce_v11_0_hw_fini()
3073 	dce_v11_0_pageflip_interrupt_fini(adev);  in dce_v11_0_hw_fini()
3080 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_suspend()  local
3082 	amdgpu_atombios_scratch_regs_save(adev);  in dce_v11_0_suspend()
3089 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_resume()  local
3094 	amdgpu_atombios_scratch_regs_restore(adev);  in dce_v11_0_resume()
3097 	if (adev->mode_info.bl_encoder) {  in dce_v11_0_resume()
3098 		u8 bl_level = amdgpu_display_backlight_get_level(adev,  in dce_v11_0_resume()
3099 								  adev->mode_info.bl_encoder);  in dce_v11_0_resume()
3100 		amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,  in dce_v11_0_resume()
3119 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_print_status()  local
3121 	dev_info(adev->dev, "DCE 10.x registers\n");  in dce_v11_0_print_status()
3128 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in dce_v11_0_soft_reset()  local
3130 	if (dce_v11_0_is_display_hung(adev))  in dce_v11_0_soft_reset()
3134 		dce_v11_0_print_status((void *)adev);  in dce_v11_0_soft_reset()
3138 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in dce_v11_0_soft_reset()
3150 		dce_v11_0_print_status((void *)adev);  in dce_v11_0_soft_reset()
3155 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,  in dce_v11_0_set_crtc_vblank_interrupt_state()  argument
3161 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v11_0_set_crtc_vblank_interrupt_state()
3184 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,  in dce_v11_0_set_crtc_vline_interrupt_state()  argument
3190 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v11_0_set_crtc_vline_interrupt_state()
3213 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,  in dce_v11_0_set_hpd_irq_state()  argument
3220 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_set_hpd_irq_state()
3243 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,  in dce_v11_0_set_crtc_irq_state()  argument
3250 		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);  in dce_v11_0_set_crtc_irq_state()
3253 		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);  in dce_v11_0_set_crtc_irq_state()
3256 		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);  in dce_v11_0_set_crtc_irq_state()
3259 		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);  in dce_v11_0_set_crtc_irq_state()
3262 		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);  in dce_v11_0_set_crtc_irq_state()
3265 		dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);  in dce_v11_0_set_crtc_irq_state()
3268 		dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);  in dce_v11_0_set_crtc_irq_state()
3271 		dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);  in dce_v11_0_set_crtc_irq_state()
3274 		dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);  in dce_v11_0_set_crtc_irq_state()
3277 		dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);  in dce_v11_0_set_crtc_irq_state()
3280 		dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);  in dce_v11_0_set_crtc_irq_state()
3283 		dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);  in dce_v11_0_set_crtc_irq_state()
3291 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,  in dce_v11_0_set_pageflip_irq_state()  argument
3298 	if (type >= adev->mode_info.num_crtc) {  in dce_v11_0_set_pageflip_irq_state()
3314 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,  in dce_v11_0_pageflip_irq()  argument
3324 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];  in dce_v11_0_pageflip_irq()
3326 	if (crtc_id >= adev->mode_info.num_crtc) {  in dce_v11_0_pageflip_irq()
3340 	spin_lock_irqsave(&adev->ddev->event_lock, flags);  in dce_v11_0_pageflip_irq()
3347 		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);  in dce_v11_0_pageflip_irq()
3357 		drm_send_vblank_event(adev->ddev, crtc_id, works->event);  in dce_v11_0_pageflip_irq()
3359 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);  in dce_v11_0_pageflip_irq()
3361 	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);  in dce_v11_0_pageflip_irq()
3367 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,  in dce_v11_0_hpd_int_ack()  argument
3372 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_int_ack()
3382 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,  in dce_v11_0_crtc_vblank_int_ack()  argument
3387 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v11_0_crtc_vblank_int_ack()
3397 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,  in dce_v11_0_crtc_vline_int_ack()  argument
3402 	if (crtc >= adev->mode_info.num_crtc) {  in dce_v11_0_crtc_vline_int_ack()
3412 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,  in dce_v11_0_crtc_irq()  argument
3418 	unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);  in dce_v11_0_crtc_irq()
3423 			dce_v11_0_crtc_vblank_int_ack(adev, crtc);  in dce_v11_0_crtc_irq()
3427 		if (amdgpu_irq_enabled(adev, source, irq_type)) {  in dce_v11_0_crtc_irq()
3428 			drm_handle_vblank(adev->ddev, crtc);  in dce_v11_0_crtc_irq()
3435 			dce_v11_0_crtc_vline_int_ack(adev, crtc);  in dce_v11_0_crtc_irq()
3450 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,  in dce_v11_0_hpd_irq()  argument
3457 	if (entry->src_data >= adev->mode_info.num_hpd) {  in dce_v11_0_hpd_irq()
3467 		dce_v11_0_hpd_int_ack(adev, hpd);  in dce_v11_0_hpd_irq()
3468 		schedule_work(&adev->hotplug_work);  in dce_v11_0_hpd_irq()
3527 	struct amdgpu_device *adev = encoder->dev->dev_private;  in dce_v11_0_encoder_prepare()  local
3539 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];  in dce_v11_0_encoder_prepare()
3543 	amdgpu_atombios_scratch_regs_lock(adev, true);  in dce_v11_0_encoder_prepare()
3567 	struct amdgpu_device *adev = dev->dev_private;  in dce_v11_0_encoder_commit()  local
3571 	amdgpu_atombios_scratch_regs_lock(adev, false);  in dce_v11_0_encoder_commit()
3670 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,  in dce_v11_0_encoder_add()  argument
3675 	struct drm_device *dev = adev->ddev;  in dce_v11_0_encoder_add()
3695 	switch (adev->mode_info.num_crtc) {  in dce_v11_0_encoder_add()
3793 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)  in dce_v11_0_set_display_funcs()  argument
3795 	if (adev->mode_info.funcs == NULL)  in dce_v11_0_set_display_funcs()
3796 		adev->mode_info.funcs = &dce_v11_0_display_funcs;  in dce_v11_0_set_display_funcs()
3814 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)  in dce_v11_0_set_irq_funcs()  argument
3816 	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;  in dce_v11_0_set_irq_funcs()
3817 	adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;  in dce_v11_0_set_irq_funcs()
3819 	adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;  in dce_v11_0_set_irq_funcs()
3820 	adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;  in dce_v11_0_set_irq_funcs()
3822 	adev->hpd_irq.num_types = AMDGPU_HPD_LAST;  in dce_v11_0_set_irq_funcs()
3823 	adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;  in dce_v11_0_set_irq_funcs()