Lines Matching refs:tmp
369 u32 tmp; in dce_v10_0_hpd_set_polarity() local
396 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); in dce_v10_0_hpd_set_polarity()
398 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); in dce_v10_0_hpd_set_polarity()
400 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); in dce_v10_0_hpd_set_polarity()
401 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); in dce_v10_0_hpd_set_polarity()
416 u32 tmp; in dce_v10_0_hpd_init() local
455 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); in dce_v10_0_hpd_init()
456 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); in dce_v10_0_hpd_init()
457 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); in dce_v10_0_hpd_init()
459 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); in dce_v10_0_hpd_init()
460 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
463 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, in dce_v10_0_hpd_init()
466 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); in dce_v10_0_hpd_init()
486 u32 tmp; in dce_v10_0_hpd_fini() local
515 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); in dce_v10_0_hpd_fini()
516 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); in dce_v10_0_hpd_fini()
517 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); in dce_v10_0_hpd_fini()
533 u32 i, j, tmp; in dce_v10_0_is_display_hung() local
536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
537 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { in dce_v10_0_is_display_hung()
546 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
547 if (tmp != crtc_status[i]) in dce_v10_0_is_display_hung()
562 u32 crtc_enabled, tmp; in dce_v10_0_stop_mc_access() local
569 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_stop_mc_access()
570 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in dce_v10_0_stop_mc_access()
571 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_stop_mc_access()
583 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v10_0_stop_mc_access()
584 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { in dce_v10_0_stop_mc_access()
587 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); in dce_v10_0_stop_mc_access()
588 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_stop_mc_access()
598 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v10_0_stop_mc_access()
599 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { in dce_v10_0_stop_mc_access()
600 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); in dce_v10_0_stop_mc_access()
601 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); in dce_v10_0_stop_mc_access()
603 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); in dce_v10_0_stop_mc_access()
604 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { in dce_v10_0_stop_mc_access()
605 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); in dce_v10_0_stop_mc_access()
606 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in dce_v10_0_stop_mc_access()
611 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_stop_mc_access()
612 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); in dce_v10_0_stop_mc_access()
613 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_stop_mc_access()
627 u32 tmp, frame_count; in dce_v10_0_resume_mc_access() local
642 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); in dce_v10_0_resume_mc_access()
643 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { in dce_v10_0_resume_mc_access()
644 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); in dce_v10_0_resume_mc_access()
645 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); in dce_v10_0_resume_mc_access()
647 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v10_0_resume_mc_access()
648 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { in dce_v10_0_resume_mc_access()
649 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); in dce_v10_0_resume_mc_access()
650 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); in dce_v10_0_resume_mc_access()
652 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); in dce_v10_0_resume_mc_access()
653 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { in dce_v10_0_resume_mc_access()
654 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); in dce_v10_0_resume_mc_access()
655 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in dce_v10_0_resume_mc_access()
658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); in dce_v10_0_resume_mc_access()
659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) in dce_v10_0_resume_mc_access()
663 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v10_0_resume_mc_access()
664 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); in dce_v10_0_resume_mc_access()
666 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_resume_mc_access()
690 u32 tmp; in dce_v10_0_set_vga_render_state() local
693 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v10_0_set_vga_render_state()
695 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v10_0_set_vga_render_state()
697 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v10_0_set_vga_render_state()
698 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
701 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
703 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); in dce_v10_0_set_vga_render_state()
705 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in dce_v10_0_set_vga_render_state()
706 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
717 u32 tmp = 0; in dce_v10_0_program_fmt() local
742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v10_0_program_fmt()
747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt()
754 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); in dce_v10_0_program_fmt()
760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); in dce_v10_0_program_fmt()
767 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
768 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
769 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
770 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); in dce_v10_0_program_fmt()
773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); in dce_v10_0_program_fmt()
782 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
803 u32 tmp, buffer_alloc, i, mem_cfg; in dce_v10_0_line_buffer_adjust() local
833 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v10_0_line_buffer_adjust()
834 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); in dce_v10_0_line_buffer_adjust()
835 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_line_buffer_adjust()
837 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
838 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v10_0_line_buffer_adjust()
839 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust()
842 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
843 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()
875 u32 tmp = RREG32(mmMC_SHARED_CHMAP); in cik_get_number_of_dram_channels() local
877 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in cik_get_number_of_dram_channels()
1107 u32 tmp, dmif_size = 12288; in dce_v10_0_latency_watermark() local
1134 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); in dce_v10_0_latency_watermark()
1142 lb_fill_bw = min(tmp, dfixed_trunc(b)); in dce_v10_0_latency_watermark()
1253 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; in dce_v10_0_program_watermarks() local
1341 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); in dce_v10_0_program_watermarks()
1342 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1343 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1344 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); in dce_v10_0_program_watermarks()
1345 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); in dce_v10_0_program_watermarks()
1346 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1348 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); in dce_v10_0_program_watermarks()
1349 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1350 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1351 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); in dce_v10_0_program_watermarks()
1352 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); in dce_v10_0_program_watermarks()
1353 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1396 u32 offset, tmp; in dce_v10_0_audio_get_connected_pins() local
1400 tmp = RREG32_AUDIO_ENDPT(offset, in dce_v10_0_audio_get_connected_pins()
1402 if (((tmp & in dce_v10_0_audio_get_connected_pins()
1430 u32 tmp; in dce_v10_0_afmt_audio_select_pin() local
1435 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1436 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1437 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1448 u32 tmp; in dce_v10_0_audio_write_latency_fields() local
1469 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1471 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1474 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1476 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, in dce_v10_0_audio_write_latency_fields()
1480 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); in dce_v10_0_audio_write_latency_fields()
1490 u32 tmp; in dce_v10_0_audio_write_speaker_allocation() local
1516 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1518 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1521 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1524 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1527 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, in dce_v10_0_audio_write_speaker_allocation()
1530 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); in dce_v10_0_audio_write_speaker_allocation()
1583 u32 tmp = 0; in dce_v10_0_audio_write_sad_regs() local
1593 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1595 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1609 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, in dce_v10_0_audio_write_sad_regs()
1611 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1690 u32 tmp; in dce_v10_0_afmt_update_ACR() local
1692 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); in dce_v10_0_afmt_update_ACR()
1694 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1695 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); in dce_v10_0_afmt_update_ACR()
1697 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1699 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1700 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); in dce_v10_0_afmt_update_ACR()
1701 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1702 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1703 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
1704 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1706 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1707 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); in dce_v10_0_afmt_update_ACR()
1708 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1709 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1710 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); in dce_v10_0_afmt_update_ACR()
1711 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1747 u32 tmp; in dce_v10_0_audio_set_dto() local
1757 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); in dce_v10_0_audio_set_dto()
1758 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, in dce_v10_0_audio_set_dto()
1760 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); in dce_v10_0_audio_set_dto()
1779 u32 tmp; in dce_v10_0_afmt_setmode() local
1801 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1802 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); in dce_v10_0_afmt_setmode()
1803 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1807 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); in dce_v10_0_afmt_setmode()
1815 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in dce_v10_0_afmt_setmode()
1820 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1821 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); in dce_v10_0_afmt_setmode()
1826 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); in dce_v10_0_afmt_setmode()
1827 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); in dce_v10_0_afmt_setmode()
1832 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1834 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1835 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when re… in dce_v10_0_afmt_setmode()
1836 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packet… in dce_v10_0_afmt_setmode()
1837 …tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packet… in dce_v10_0_afmt_setmode()
1838 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1842 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in dce_v10_0_afmt_setmode()
1844 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); in dce_v10_0_afmt_setmode()
1845 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1847 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1849 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in dce_v10_0_afmt_setmode()
1850 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1852 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1854 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); in dce_v10_0_afmt_setmode()
1855 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1859 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1861 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); in dce_v10_0_afmt_setmode()
1863 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); in dce_v10_0_afmt_setmode()
1864 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1866 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1868 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in dce_v10_0_afmt_setmode()
1869 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1871 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1874 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); in dce_v10_0_afmt_setmode()
1877 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); in dce_v10_0_afmt_setmode()
1879 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); in dce_v10_0_afmt_setmode()
1880 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1884 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1885 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); in dce_v10_0_afmt_setmode()
1886 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1888 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1889 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in dce_v10_0_afmt_setmode()
1890 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1892 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1893 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); in dce_v10_0_afmt_setmode()
1894 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); in dce_v10_0_afmt_setmode()
1895 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); in dce_v10_0_afmt_setmode()
1896 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); in dce_v10_0_afmt_setmode()
1897 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); in dce_v10_0_afmt_setmode()
1898 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); in dce_v10_0_afmt_setmode()
1899 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1924 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1926 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); in dce_v10_0_afmt_setmode()
1928 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); in dce_v10_0_afmt_setmode()
1929 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1931 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1932 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); in dce_v10_0_afmt_setmode()
1933 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1935 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1937 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); in dce_v10_0_afmt_setmode()
1938 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
2054 u32 tmp, viewport_w, viewport_h; in dce_v10_0_crtc_do_set_base() local
2220 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2222 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); in dce_v10_0_crtc_do_set_base()
2224 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); in dce_v10_0_crtc_do_set_base()
2225 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, in dce_v10_0_crtc_do_set_base()
2259 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2286 u32 tmp; in dce_v10_0_set_interleave() local
2288 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v10_0_set_interleave()
2290 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); in dce_v10_0_set_interleave()
2292 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); in dce_v10_0_set_interleave()
2293 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_set_interleave()
2302 u32 tmp; in dce_v10_0_crtc_load_lut() local
2306 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2307 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); in dce_v10_0_crtc_load_lut()
2308 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); in dce_v10_0_crtc_load_lut()
2309 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2311 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2312 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_v10_0_crtc_load_lut()
2313 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2315 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2316 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); in dce_v10_0_crtc_load_lut()
2317 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2319 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2320 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2321 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2322 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2345 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2346 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2347 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2348 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2349 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2351 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2352 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); in dce_v10_0_crtc_load_lut()
2353 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); in dce_v10_0_crtc_load_lut()
2354 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2356 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2357 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2358 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); in dce_v10_0_crtc_load_lut()
2359 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2361 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2362 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); in dce_v10_0_crtc_load_lut()
2363 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); in dce_v10_0_crtc_load_lut()
2364 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2371 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2372 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); in dce_v10_0_crtc_load_lut()
2373 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2486 u32 tmp; in dce_v10_0_hide_cursor() local
2488 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_hide_cursor()
2489 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); in dce_v10_0_hide_cursor()
2490 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2497 u32 tmp; in dce_v10_0_show_cursor() local
2504 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_show_cursor()
2505 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); in dce_v10_0_show_cursor()
2506 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); in dce_v10_0_show_cursor()
2507 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()
3134 u32 srbm_soft_reset = 0, tmp; in dce_v10_0_soft_reset() local
3143 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
3144 tmp |= srbm_soft_reset; in dce_v10_0_soft_reset()
3145 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v10_0_soft_reset()
3146 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset()
3147 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
3151 tmp &= ~srbm_soft_reset; in dce_v10_0_soft_reset()
3152 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset()
3153 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
3225 u32 tmp; in dce_v10_0_set_hpd_irq_state() local
3234 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3235 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); in dce_v10_0_set_hpd_irq_state()
3236 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3239 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3240 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); in dce_v10_0_set_hpd_irq_state()
3241 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3377 u32 tmp; in dce_v10_0_hpd_int_ack() local
3384 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3385 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); in dce_v10_0_hpd_int_ack()
3386 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3392 u32 tmp; in dce_v10_0_crtc_vblank_int_ack() local
3399 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vblank_int_ack()
3400 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); in dce_v10_0_crtc_vblank_int_ack()
3401 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vblank_int_ack()
3407 u32 tmp; in dce_v10_0_crtc_vline_int_ack() local
3414 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vline_int_ack()
3415 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); in dce_v10_0_crtc_vline_int_ack()
3416 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vline_int_ack()