414 	struct drm_device *dev = adev->ddev;  in dce_v10_0_hpd_init()
484 	struct drm_device *dev = adev->ddev;  in dce_v10_0_hpd_fini()
2889 	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);  in dce_v10_0_crtc_init()
2898 	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;  in dce_v10_0_crtc_init()
2899 	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;  in dce_v10_0_crtc_init()
2987 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;  in dce_v10_0_sw_init()
2989 	adev->ddev->mode_config.max_width = 16384;  in dce_v10_0_sw_init()
2990 	adev->ddev->mode_config.max_height = 16384;  in dce_v10_0_sw_init()
2992 	adev->ddev->mode_config.preferred_depth = 24;  in dce_v10_0_sw_init()
2993 	adev->ddev->mode_config.prefer_shadow = 1;  in dce_v10_0_sw_init()
2995 	adev->ddev->mode_config.fb_base = adev->mc.aper_base;  in dce_v10_0_sw_init()
3001 	adev->ddev->mode_config.max_width = 16384;  in dce_v10_0_sw_init()
3002 	adev->ddev->mode_config.max_height = 16384;  in dce_v10_0_sw_init()
3012 		amdgpu_print_display_setup(adev->ddev);  in dce_v10_0_sw_init()
3023 	drm_kms_helper_poll_init(adev->ddev);  in dce_v10_0_sw_init()
3034 	drm_kms_helper_poll_fini(adev->ddev);  in dce_v10_0_sw_fini()
3040 	drm_mode_config_cleanup(adev->ddev);  in dce_v10_0_sw_fini()
3347 	spin_lock_irqsave(&adev->ddev->event_lock, flags);  in dce_v10_0_pageflip_irq()
3354 		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);  in dce_v10_0_pageflip_irq()
3364 		drm_send_vblank_event(adev->ddev, crtc_id, works->event);  in dce_v10_0_pageflip_irq()
3366 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);  in dce_v10_0_pageflip_irq()
3368 	drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);  in dce_v10_0_pageflip_irq()
3435 			drm_handle_vblank(adev->ddev, crtc);  in dce_v10_0_crtc_irq()
3682 	struct drm_device *dev = adev->ddev;  in dce_v10_0_encoder_add()