Lines Matching refs:adev
43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) in dce_v10_0_init_golden_registers() argument
145 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
147 amdgpu_program_register_sequence(adev, in dce_v10_0_init_golden_registers()
150 amdgpu_program_register_sequence(adev, in dce_v10_0_init_golden_registers()
155 amdgpu_program_register_sequence(adev, in dce_v10_0_init_golden_registers()
158 amdgpu_program_register_sequence(adev, in dce_v10_0_init_golden_registers()
167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, in dce_v10_0_audio_endpt_rreg() argument
173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, in dce_v10_0_audio_endpt_wreg() argument
186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) in dce_v10_0_is_in_vblank() argument
201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) in dce_v10_0_is_counter_moving() argument
222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) in dce_v10_0_vblank_wait() argument
226 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_wait()
235 while (dce_v10_0_is_in_vblank(adev, crtc)) { in dce_v10_0_vblank_wait()
237 if (!dce_v10_0_is_counter_moving(adev, crtc)) in dce_v10_0_vblank_wait()
242 while (!dce_v10_0_is_in_vblank(adev, crtc)) { in dce_v10_0_vblank_wait()
244 if (!dce_v10_0_is_counter_moving(adev, crtc)) in dce_v10_0_vblank_wait()
250 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) in dce_v10_0_vblank_get_counter() argument
252 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
258 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) in dce_v10_0_pageflip_interrupt_init() argument
263 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_init()
264 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_init()
267 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) in dce_v10_0_pageflip_interrupt_fini() argument
272 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_fini()
273 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_fini()
286 static void dce_v10_0_page_flip(struct amdgpu_device *adev, in dce_v10_0_page_flip() argument
289 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip()
301 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, in dce_v10_0_crtc_get_scanoutpos() argument
304 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v10_0_crtc_get_scanoutpos()
322 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, in dce_v10_0_hpd_sense() argument
366 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, in dce_v10_0_hpd_set_polarity() argument
370 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
412 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) in dce_v10_0_hpd_init() argument
414 struct drm_device *dev = adev->ddev; in dce_v10_0_hpd_init()
468 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
469 amdgpu_irq_get(adev, &adev->hpd_irq, in dce_v10_0_hpd_init()
482 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) in dce_v10_0_hpd_fini() argument
484 struct drm_device *dev = adev->ddev; in dce_v10_0_hpd_fini()
519 amdgpu_irq_put(adev, &adev->hpd_irq, in dce_v10_0_hpd_fini()
524 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) in dce_v10_0_hpd_get_gpio_reg() argument
529 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) in dce_v10_0_is_display_hung() argument
535 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
544 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
559 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, in dce_v10_0_stop_mc_access() argument
574 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_stop_mc_access()
585 amdgpu_display_vblank_wait(adev, i); in dce_v10_0_stop_mc_access()
592 frame_count = amdgpu_display_vblank_get_counter(adev, i); in dce_v10_0_stop_mc_access()
593 for (j = 0; j < adev->usec_timeout; j++) { in dce_v10_0_stop_mc_access()
594 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) in dce_v10_0_stop_mc_access()
624 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, in dce_v10_0_resume_mc_access() argument
631 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_resume_mc_access()
633 upper_32_bits(adev->mc.vram_start)); in dce_v10_0_resume_mc_access()
635 upper_32_bits(adev->mc.vram_start)); in dce_v10_0_resume_mc_access()
637 (u32)adev->mc.vram_start); in dce_v10_0_resume_mc_access()
639 (u32)adev->mc.vram_start); in dce_v10_0_resume_mc_access()
657 for (j = 0; j < adev->usec_timeout; j++) { in dce_v10_0_resume_mc_access()
669 frame_count = amdgpu_display_vblank_get_counter(adev, i); in dce_v10_0_resume_mc_access()
670 for (j = 0; j < adev->usec_timeout; j++) { in dce_v10_0_resume_mc_access()
671 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) in dce_v10_0_resume_mc_access()
678 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); in dce_v10_0_resume_mc_access()
679 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); in dce_v10_0_resume_mc_access()
687 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, in dce_v10_0_set_vga_render_state() argument
712 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_program_fmt() local
799 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, in dce_v10_0_line_buffer_adjust() argument
822 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
826 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
841 for (i = 0; i < adev->usec_timeout; i++) { in dce_v10_0_line_buffer_adjust()
873 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) in cik_get_number_of_dram_channels() argument
1244 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, in dce_v10_0_program_watermarks() argument
1260 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1262 amdgpu_dpm_get_mclk(adev, false) * 10; in dce_v10_0_program_watermarks()
1264 amdgpu_dpm_get_sclk(adev, false) * 10; in dce_v10_0_program_watermarks()
1266 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1267 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1283 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); in dce_v10_0_program_watermarks()
1294 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1299 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1301 amdgpu_dpm_get_mclk(adev, true) * 10; in dce_v10_0_program_watermarks()
1303 amdgpu_dpm_get_sclk(adev, true) * 10; in dce_v10_0_program_watermarks()
1305 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1306 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1322 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); in dce_v10_0_program_watermarks()
1333 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1373 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) in dce_v10_0_bandwidth_update() argument
1379 amdgpu_update_display_priority(adev); in dce_v10_0_bandwidth_update()
1381 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1382 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update()
1385 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1386 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update()
1387 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1388 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update()
1393 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) in dce_v10_0_audio_get_connected_pins() argument
1398 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_connected_pins()
1399 offset = adev->mode_info.audio.pin[i].offset; in dce_v10_0_audio_get_connected_pins()
1405 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_get_connected_pins()
1407 adev->mode_info.audio.pin[i].connected = true; in dce_v10_0_audio_get_connected_pins()
1411 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) in dce_v10_0_audio_get_pin() argument
1415 dce_v10_0_audio_get_connected_pins(adev); in dce_v10_0_audio_get_pin()
1417 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_pin()
1418 if (adev->mode_info.audio.pin[i].connected) in dce_v10_0_audio_get_pin()
1419 return &adev->mode_info.audio.pin[i]; in dce_v10_0_audio_get_pin()
1427 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v10_0_afmt_audio_select_pin() local
1443 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v10_0_audio_write_latency_fields() local
1485 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v10_0_audio_write_speaker_allocation() local
1537 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v10_0_audio_write_sad_regs() local
1617 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, in dce_v10_0_audio_enable() argument
1639 static int dce_v10_0_audio_init(struct amdgpu_device *adev) in dce_v10_0_audio_init() argument
1646 adev->mode_info.audio.enabled = true; in dce_v10_0_audio_init()
1648 adev->mode_info.audio.num_pins = 7; in dce_v10_0_audio_init()
1650 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_init()
1651 adev->mode_info.audio.pin[i].channels = -1; in dce_v10_0_audio_init()
1652 adev->mode_info.audio.pin[i].rate = -1; in dce_v10_0_audio_init()
1653 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v10_0_audio_init()
1654 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v10_0_audio_init()
1655 adev->mode_info.audio.pin[i].category_code = 0; in dce_v10_0_audio_init()
1656 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_init()
1657 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v10_0_audio_init()
1658 adev->mode_info.audio.pin[i].id = i; in dce_v10_0_audio_init()
1661 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_init()
1667 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) in dce_v10_0_audio_fini() argument
1671 if (!adev->mode_info.audio.enabled) in dce_v10_0_audio_fini()
1674 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v10_0_audio_fini()
1675 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_fini()
1677 adev->mode_info.audio.enabled = false; in dce_v10_0_audio_fini()
1686 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_afmt_update_ACR() local
1722 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_afmt_update_avi_infoframe() local
1741 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_audio_set_dto() local
1772 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_afmt_setmode() local
1796 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1797 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1946 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1952 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_afmt_enable() local
1966 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1976 static void dce_v10_0_afmt_init(struct amdgpu_device *adev) in dce_v10_0_afmt_init() argument
1980 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v10_0_afmt_init()
1981 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_init()
1984 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_init()
1985 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v10_0_afmt_init()
1986 if (adev->mode_info.afmt[i]) { in dce_v10_0_afmt_init()
1987 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v10_0_afmt_init()
1988 adev->mode_info.afmt[i]->id = i; in dce_v10_0_afmt_init()
1993 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) in dce_v10_0_afmt_fini() argument
1997 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_fini()
1998 kfree(adev->mode_info.afmt[i]); in dce_v10_0_afmt_fini()
1999 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_fini()
2017 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_vga_enable() local
2031 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_grph_enable() local
2045 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_crtc_do_set_base() local
2275 dce_v10_0_bandwidth_update(adev); in dce_v10_0_crtc_do_set_base()
2284 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_set_interleave() local
2300 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_crtc_load_lut() local
2435 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_pick_pll() local
2440 if (adev->clock.dp_extclk) in dce_v10_0_pick_pll()
2470 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_lock_cursor() local
2485 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_hide_cursor() local
2496 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_show_cursor() local
2514 struct amdgpu_device *adev = crtc->dev->dev_private; in dce_v10_0_cursor_move_locked() local
2689 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_crtc_dpms() local
2701 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); in dce_v10_0_crtc_dpms()
2702 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v10_0_crtc_dpms()
2703 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v10_0_crtc_dpms()
2721 amdgpu_pm_compute_clocks(adev); in dce_v10_0_crtc_dpms()
2742 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_crtc_disable() local
2767 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_crtc_disable()
2768 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable()
2769 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable()
2771 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2879 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) in dce_v10_0_crtc_init() argument
2889 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); in dce_v10_0_crtc_init()
2894 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
2898 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v10_0_crtc_init()
2899 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v10_0_crtc_init()
2940 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_early_init() local
2942 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; in dce_v10_0_early_init()
2943 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; in dce_v10_0_early_init()
2945 dce_v10_0_set_display_funcs(adev); in dce_v10_0_early_init()
2946 dce_v10_0_set_irq_funcs(adev); in dce_v10_0_early_init()
2948 switch (adev->asic_type) { in dce_v10_0_early_init()
2951 adev->mode_info.num_crtc = 6; /* XXX 7??? */ in dce_v10_0_early_init()
2952 adev->mode_info.num_hpd = 6; in dce_v10_0_early_init()
2953 adev->mode_info.num_dig = 7; in dce_v10_0_early_init()
2966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_sw_init() local
2968 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2969 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); in dce_v10_0_sw_init()
2975 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); in dce_v10_0_sw_init()
2981 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); in dce_v10_0_sw_init()
2985 adev->mode_info.mode_config_initialized = true; in dce_v10_0_sw_init()
2987 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; in dce_v10_0_sw_init()
2989 adev->ddev->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2990 adev->ddev->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2992 adev->ddev->mode_config.preferred_depth = 24; in dce_v10_0_sw_init()
2993 adev->ddev->mode_config.prefer_shadow = 1; in dce_v10_0_sw_init()
2995 adev->ddev->mode_config.fb_base = adev->mc.aper_base; in dce_v10_0_sw_init()
2997 r = amdgpu_modeset_create_props(adev); in dce_v10_0_sw_init()
3001 adev->ddev->mode_config.max_width = 16384; in dce_v10_0_sw_init()
3002 adev->ddev->mode_config.max_height = 16384; in dce_v10_0_sw_init()
3005 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
3006 r = dce_v10_0_crtc_init(adev, i); in dce_v10_0_sw_init()
3011 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) in dce_v10_0_sw_init()
3012 amdgpu_print_display_setup(adev->ddev); in dce_v10_0_sw_init()
3017 dce_v10_0_afmt_init(adev); in dce_v10_0_sw_init()
3019 r = dce_v10_0_audio_init(adev); in dce_v10_0_sw_init()
3023 drm_kms_helper_poll_init(adev->ddev); in dce_v10_0_sw_init()
3030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_sw_fini() local
3032 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v10_0_sw_fini()
3034 drm_kms_helper_poll_fini(adev->ddev); in dce_v10_0_sw_fini()
3036 dce_v10_0_audio_fini(adev); in dce_v10_0_sw_fini()
3038 dce_v10_0_afmt_fini(adev); in dce_v10_0_sw_fini()
3040 drm_mode_config_cleanup(adev->ddev); in dce_v10_0_sw_fini()
3041 adev->mode_info.mode_config_initialized = false; in dce_v10_0_sw_fini()
3049 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_hw_init() local
3051 dce_v10_0_init_golden_registers(adev); in dce_v10_0_hw_init()
3054 amdgpu_atombios_encoder_init_dig(adev); in dce_v10_0_hw_init()
3055 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v10_0_hw_init()
3058 dce_v10_0_hpd_init(adev); in dce_v10_0_hw_init()
3060 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_init()
3061 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_init()
3064 dce_v10_0_pageflip_interrupt_init(adev); in dce_v10_0_hw_init()
3072 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_hw_fini() local
3074 dce_v10_0_hpd_fini(adev); in dce_v10_0_hw_fini()
3076 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_fini()
3077 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_fini()
3080 dce_v10_0_pageflip_interrupt_fini(adev); in dce_v10_0_hw_fini()
3087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_suspend() local
3089 amdgpu_atombios_scratch_regs_save(adev); in dce_v10_0_suspend()
3096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_resume() local
3101 amdgpu_atombios_scratch_regs_restore(adev); in dce_v10_0_resume()
3104 if (adev->mode_info.bl_encoder) { in dce_v10_0_resume()
3105 u8 bl_level = amdgpu_display_backlight_get_level(adev, in dce_v10_0_resume()
3106 adev->mode_info.bl_encoder); in dce_v10_0_resume()
3107 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v10_0_resume()
3126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_print_status() local
3128 dev_info(adev->dev, "DCE 10.x registers\n"); in dce_v10_0_print_status()
3135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in dce_v10_0_soft_reset() local
3137 if (dce_v10_0_is_display_hung(adev)) in dce_v10_0_soft_reset()
3141 dce_v10_0_print_status((void *)adev); in dce_v10_0_soft_reset()
3145 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v10_0_soft_reset()
3157 dce_v10_0_print_status((void *)adev); in dce_v10_0_soft_reset()
3162 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, in dce_v10_0_set_crtc_vblank_interrupt_state() argument
3168 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vblank_interrupt_state()
3191 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, in dce_v10_0_set_crtc_vline_interrupt_state() argument
3197 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vline_interrupt_state()
3220 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, in dce_v10_0_set_hpd_irq_state() argument
3227 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3250 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, in dce_v10_0_set_crtc_irq_state() argument
3257 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); in dce_v10_0_set_crtc_irq_state()
3260 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); in dce_v10_0_set_crtc_irq_state()
3263 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); in dce_v10_0_set_crtc_irq_state()
3266 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); in dce_v10_0_set_crtc_irq_state()
3269 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); in dce_v10_0_set_crtc_irq_state()
3272 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); in dce_v10_0_set_crtc_irq_state()
3275 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); in dce_v10_0_set_crtc_irq_state()
3278 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); in dce_v10_0_set_crtc_irq_state()
3281 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); in dce_v10_0_set_crtc_irq_state()
3284 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); in dce_v10_0_set_crtc_irq_state()
3287 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); in dce_v10_0_set_crtc_irq_state()
3290 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); in dce_v10_0_set_crtc_irq_state()
3298 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, in dce_v10_0_set_pageflip_irq_state() argument
3305 if (type >= adev->mode_info.num_crtc) { in dce_v10_0_set_pageflip_irq_state()
3321 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, in dce_v10_0_pageflip_irq() argument
3331 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
3333 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v10_0_pageflip_irq()
3347 spin_lock_irqsave(&adev->ddev->event_lock, flags); in dce_v10_0_pageflip_irq()
3354 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); in dce_v10_0_pageflip_irq()
3364 drm_send_vblank_event(adev->ddev, crtc_id, works->event); in dce_v10_0_pageflip_irq()
3366 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); in dce_v10_0_pageflip_irq()
3368 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); in dce_v10_0_pageflip_irq()
3374 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, in dce_v10_0_hpd_int_ack() argument
3379 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3389 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, in dce_v10_0_crtc_vblank_int_ack() argument
3394 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vblank_int_ack()
3404 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, in dce_v10_0_crtc_vline_int_ack() argument
3409 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vline_int_ack()
3419 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, in dce_v10_0_crtc_irq() argument
3425 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); in dce_v10_0_crtc_irq()
3430 dce_v10_0_crtc_vblank_int_ack(adev, crtc); in dce_v10_0_crtc_irq()
3434 if (amdgpu_irq_enabled(adev, source, irq_type)) { in dce_v10_0_crtc_irq()
3435 drm_handle_vblank(adev->ddev, crtc); in dce_v10_0_crtc_irq()
3442 dce_v10_0_crtc_vline_int_ack(adev, crtc); in dce_v10_0_crtc_irq()
3457 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, in dce_v10_0_hpd_irq() argument
3464 if (entry->src_data >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_irq()
3474 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3475 schedule_work(&adev->hotplug_work); in dce_v10_0_hpd_irq()
3534 struct amdgpu_device *adev = encoder->dev->dev_private; in dce_v10_0_encoder_prepare() local
3546 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()
3550 amdgpu_atombios_scratch_regs_lock(adev, true); in dce_v10_0_encoder_prepare()
3574 struct amdgpu_device *adev = dev->dev_private; in dce_v10_0_encoder_commit() local
3578 amdgpu_atombios_scratch_regs_lock(adev, false); in dce_v10_0_encoder_commit()
3677 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, in dce_v10_0_encoder_add() argument
3682 struct drm_device *dev = adev->ddev; in dce_v10_0_encoder_add()
3702 switch (adev->mode_info.num_crtc) { in dce_v10_0_encoder_add()
3800 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) in dce_v10_0_set_display_funcs() argument
3802 if (adev->mode_info.funcs == NULL) in dce_v10_0_set_display_funcs()
3803 adev->mode_info.funcs = &dce_v10_0_display_funcs; in dce_v10_0_set_display_funcs()
3821 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) in dce_v10_0_set_irq_funcs() argument
3823 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; in dce_v10_0_set_irq_funcs()
3824 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; in dce_v10_0_set_irq_funcs()
3826 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; in dce_v10_0_set_irq_funcs()
3827 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; in dce_v10_0_set_irq_funcs()
3829 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; in dce_v10_0_set_irq_funcs()
3830 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; in dce_v10_0_set_irq_funcs()