Lines Matching refs:uint32_t
67 uint32_t offset;
68 uint32_t mask;
69 uint32_t shift;
70 uint32_t value;
75 uint32_t soft_min_clk;
76 uint32_t hard_min_clk;
77 uint32_t soft_max_clk;
78 uint32_t hard_max_clk;
82 uint32_t sclk;
94 uint32_t num_levels;
116 uint32_t bootup_uma_clk;
117 uint32_t bootup_sclk;
118 uint32_t dentist_vco_freq;
119 uint32_t nb_dpm_enable;
120 uint32_t nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK];
121 uint32_t nbp_n_clock[CZ_NUM_NBPSTATES];
123 uint32_t display_clock[CZ_MAX_DISPLAY_CLOCK_LEVEL];
127 uint32_t uma_channel_number;
131 uint32_t active_target[CZ_MAX_HARDWARE_POWERLEVELS];
136 uint32_t lowest_valid;
137 uint32_t highest_valid;
140 uint32_t sram_end;
141 uint32_t dpm_table_start;
142 uint32_t soft_regs_start;
147 uint32_t fps_high_threshold;
148 uint32_t fps_low_threshold;
150 uint32_t dpm_flags;
170 uint32_t low_sclk_interrupt_threshold;
175 uint32_t active_process_mask;
177 uint32_t mgcg_cgtt_local0;
178 uint32_t mgcg_cgtt_local1;
179 uint32_t clock_slow_down_step;
180 uint32_t skip_clock_slow_down;
182 uint32_t voting_clients;
183 uint32_t voltage_drop_threshold;
184 uint32_t gfx_pg_threshold;
185 uint32_t max_sclk_level;
229 uint32_t cz_get_argument(struct amdgpu_device *adev);
232 uint16_t msg, uint32_t parameter);
234 uint32_t smc_address, uint32_t *value, uint32_t limit);