57 	struct cz_power_info *pi = adev->pm.dpm.priv;  in cz_get_pi()
75 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_construct_max_power_limits_table()
167 			&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);  in cz_parse_sys_info_table()
177 		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;  in cz_patch_voltage_values()
179 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in cz_patch_voltage_values()
181 		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;  in cz_patch_voltage_values()
244 			&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_parse_pplib_clock_info()
278 		adev->pm.dpm.boot_ps = rps;  in cz_parse_pplib_non_clock_info()
282 		adev->pm.dpm.uvd_ps = rps;  in cz_parse_pplib_non_clock_info()
331 	adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *  in cz_parse_power_table()
334 	if (!adev->pm.dpm.ps)  in cz_parse_power_table()
338 	adev->pm.dpm.platform_caps =  in cz_parse_power_table()
340 	adev->pm.dpm.backbias_response_time =  in cz_parse_power_table()
342 	adev->pm.dpm.voltage_response_time =  in cz_parse_power_table()
353 			kfree(adev->pm.dpm.ps);  in cz_parse_power_table()
357 		adev->pm.dpm.ps[i].ps_priv = ps;  in cz_parse_power_table()
368 			cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],  in cz_parse_power_table()
372 		cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],  in cz_parse_power_table()
377 	adev->pm.dpm.num_ps = state_array->ucNumEntries;  in cz_parse_power_table()
408 	adev->pm.dpm.priv = pi;  in cz_dpm_init()
489 	for (i = 0; i < adev->pm.dpm.num_ps; i++)  in cz_dpm_fini()
490 		kfree(adev->pm.dpm.ps[i].ps_priv);  in cz_dpm_fini()
492 	kfree(adev->pm.dpm.ps);  in cz_dpm_fini()
493 	kfree(adev->pm.dpm.priv);  in cz_dpm_fini()
510 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_dpm_debugfs_print_current_performance_level()
512 		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;  in cz_dpm_debugfs_print_current_performance_level()
514 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in cz_dpm_debugfs_print_current_performance_level()
620 	adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;  in cz_dpm_sw_init()
621 	adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;  in cz_dpm_sw_init()
622 	adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;  in cz_dpm_sw_init()
623 	adev->pm.default_sclk = adev->clock.default_sclk;  in cz_dpm_sw_init()
624 	adev->pm.default_mclk = adev->clock.default_mclk;  in cz_dpm_sw_init()
625 	adev->pm.current_sclk = adev->clock.default_sclk;  in cz_dpm_sw_init()
626 	adev->pm.current_mclk = adev->clock.default_mclk;  in cz_dpm_sw_init()
627 	adev->pm.int_thermal_type = THERMAL_TYPE_NONE;  in cz_dpm_sw_init()
632 	mutex_lock(&adev->pm.mutex);  in cz_dpm_sw_init()
637 	adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;  in cz_dpm_sw_init()
641 	mutex_unlock(&adev->pm.mutex);  in cz_dpm_sw_init()
648 	mutex_unlock(&adev->pm.mutex);  in cz_dpm_sw_init()
658 	mutex_lock(&adev->pm.mutex);  in cz_dpm_sw_fini()
661 	mutex_unlock(&adev->pm.mutex);  in cz_dpm_sw_fini()
694 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_dpm_upload_pptable_to_smu()
696 		&adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;  in cz_dpm_upload_pptable_to_smu()
698 		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;  in cz_dpm_upload_pptable_to_smu()
700 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in cz_dpm_upload_pptable_to_smu()
702 		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;  in cz_dpm_upload_pptable_to_smu()
809 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_init_sclk_limit()
837 		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;  in cz_init_uvd_limit()
865 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in cz_init_vce_limit()
894 		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;  in cz_init_acp_limit()
1008 	if (amdgpu_dpm && adev->pm.dpm_enabled) {  in cz_stop_dpm()
1025 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_get_sclk_level()
1056 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in cz_get_eclk_level()
1242 		&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in cz_apply_state_adjust_rules()
1308 	cz_update_current_ps(adev, adev->pm.dpm.boot_ps);  in cz_dpm_enable()
1318 	mutex_lock(&adev->pm.mutex);  in cz_dpm_hw_init()
1327 		mutex_unlock(&adev->pm.mutex);  in cz_dpm_hw_init()
1335 		mutex_unlock(&adev->pm.mutex);  in cz_dpm_hw_init()
1340 		adev->pm.dpm_enabled = false;  in cz_dpm_hw_init()
1341 		mutex_unlock(&adev->pm.mutex);  in cz_dpm_hw_init()
1351 		adev->pm.dpm_enabled = false;  in cz_dpm_hw_init()
1353 		adev->pm.dpm_enabled = true;  in cz_dpm_hw_init()
1355 	mutex_unlock(&adev->pm.mutex);  in cz_dpm_hw_init()
1379 	cz_update_current_ps(adev, adev->pm.dpm.boot_ps);  in cz_dpm_disable()
1389 	mutex_lock(&adev->pm.mutex);  in cz_dpm_hw_fini()
1397 	if (adev->pm.dpm_enabled) {  in cz_dpm_hw_fini()
1400 		adev->pm.dpm.current_ps =  in cz_dpm_hw_fini()
1401 			adev->pm.dpm.requested_ps =  in cz_dpm_hw_fini()
1402 			adev->pm.dpm.boot_ps;  in cz_dpm_hw_fini()
1405 	adev->pm.dpm_enabled = false;  in cz_dpm_hw_fini()
1407 	mutex_unlock(&adev->pm.mutex);  in cz_dpm_hw_fini()
1417 	if (adev->pm.dpm_enabled) {  in cz_dpm_suspend()
1418 		mutex_lock(&adev->pm.mutex);  in cz_dpm_suspend()
1422 		adev->pm.dpm.current_ps =  in cz_dpm_suspend()
1423 			adev->pm.dpm.requested_ps =  in cz_dpm_suspend()
1424 			adev->pm.dpm.boot_ps;  in cz_dpm_suspend()
1426 		mutex_unlock(&adev->pm.mutex);  in cz_dpm_suspend()
1437 	mutex_lock(&adev->pm.mutex);  in cz_dpm_resume()
1443 		mutex_unlock(&adev->pm.mutex);  in cz_dpm_resume()
1448 		adev->pm.dpm_enabled = false;  in cz_dpm_resume()
1449 		mutex_unlock(&adev->pm.mutex);  in cz_dpm_resume()
1459 		adev->pm.dpm_enabled = false;  in cz_dpm_resume()
1461 		adev->pm.dpm_enabled = true;  in cz_dpm_resume()
1463 	mutex_unlock(&adev->pm.mutex);  in cz_dpm_resume()
1465 	if (adev->pm.dpm_enabled)  in cz_dpm_resume()
1498 	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;  in cz_dpm_pre_set_power_state()
1512 		&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in cz_dpm_update_sclk_limit()
1705 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in cz_dpm_unforce_dpm_levels()
1773 	adev->pm.dpm.forced_level = level;  in cz_dpm_force_dpm_level()
1901 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in cz_update_vce_dpm()
2000 	if (NULL == adev->pm.funcs)  in cz_dpm_set_funcs()
2001 		adev->pm.funcs = &cz_dpm_funcs;  in cz_dpm_set_funcs()