Lines Matching refs:dyn_state
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_construct_max_power_limits_table()
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in cz_parse_sys_info_table()
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_patch_voltage_values()
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_patch_voltage_values()
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_patch_voltage_values()
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_parse_pplib_clock_info()
510 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_dpm_debugfs_print_current_performance_level()
512 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_dpm_debugfs_print_current_performance_level()
514 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_dpm_debugfs_print_current_performance_level()
694 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_dpm_upload_pptable_to_smu()
696 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk; in cz_dpm_upload_pptable_to_smu()
698 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_dpm_upload_pptable_to_smu()
700 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_dpm_upload_pptable_to_smu()
702 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_dpm_upload_pptable_to_smu()
809 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_init_sclk_limit()
837 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_init_uvd_limit()
865 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_init_vce_limit()
894 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_init_acp_limit()
1025 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_get_sclk_level()
1056 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_get_eclk_level()
1242 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in cz_apply_state_adjust_rules()
1512 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in cz_dpm_update_sclk_limit()
1705 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_dpm_unforce_dpm_levels()
1901 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_update_vce_dpm()