Lines Matching refs:adev
45 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
46 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
55 static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev) in cz_get_pi() argument
57 struct cz_power_info *pi = adev->pm.dpm.priv; in cz_get_pi()
62 static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev, in cz_convert_8bit_index_to_voltage() argument
70 static void cz_construct_max_power_limits_table(struct amdgpu_device *adev, in cz_construct_max_power_limits_table() argument
73 struct cz_power_info *pi = cz_get_pi(adev); in cz_construct_max_power_limits_table()
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_construct_max_power_limits_table()
79 table->vddc = cz_convert_8bit_index_to_voltage(adev, in cz_construct_max_power_limits_table()
94 static int cz_parse_sys_info_table(struct amdgpu_device *adev) in cz_parse_sys_info_table() argument
96 struct cz_power_info *pi = cz_get_pi(adev); in cz_parse_sys_info_table()
97 struct amdgpu_mode_info *mode_info = &adev->mode_info; in cz_parse_sys_info_table()
166 cz_construct_max_power_limits_table(adev, in cz_parse_sys_info_table()
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in cz_parse_sys_info_table()
173 static void cz_patch_voltage_values(struct amdgpu_device *adev) in cz_patch_voltage_values() argument
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_patch_voltage_values()
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_patch_voltage_values()
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_patch_voltage_values()
186 cz_convert_8bit_index_to_voltage(adev, in cz_patch_voltage_values()
193 cz_convert_8bit_index_to_voltage(adev, in cz_patch_voltage_values()
200 cz_convert_8bit_index_to_voltage(adev, in cz_patch_voltage_values()
206 static void cz_construct_boot_state(struct amdgpu_device *adev) in cz_construct_boot_state() argument
208 struct cz_power_info *pi = cz_get_pi(adev); in cz_construct_boot_state()
221 static void cz_patch_boot_state(struct amdgpu_device *adev, in cz_patch_boot_state() argument
224 struct cz_power_info *pi = cz_get_pi(adev); in cz_patch_boot_state()
236 static void cz_parse_pplib_clock_info(struct amdgpu_device *adev, in cz_parse_pplib_clock_info() argument
240 struct cz_power_info *pi = cz_get_pi(adev); in cz_parse_pplib_clock_info()
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_parse_pplib_clock_info()
258 static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev, in cz_parse_pplib_non_clock_info() argument
278 adev->pm.dpm.boot_ps = rps; in cz_parse_pplib_non_clock_info()
279 cz_patch_boot_state(adev, ps); in cz_parse_pplib_non_clock_info()
282 adev->pm.dpm.uvd_ps = rps; in cz_parse_pplib_non_clock_info()
299 static int cz_parse_power_table(struct amdgpu_device *adev) in cz_parse_power_table() argument
301 struct amdgpu_mode_info *mode_info = &adev->mode_info; in cz_parse_power_table()
331 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * in cz_parse_power_table()
334 if (!adev->pm.dpm.ps) in cz_parse_power_table()
338 adev->pm.dpm.platform_caps = in cz_parse_power_table()
340 adev->pm.dpm.backbias_response_time = in cz_parse_power_table()
342 adev->pm.dpm.voltage_response_time = in cz_parse_power_table()
353 kfree(adev->pm.dpm.ps); in cz_parse_power_table()
357 adev->pm.dpm.ps[i].ps_priv = ps; in cz_parse_power_table()
368 cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i], in cz_parse_power_table()
372 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in cz_parse_power_table()
377 adev->pm.dpm.num_ps = state_array->ucNumEntries; in cz_parse_power_table()
382 static int cz_process_firmware_header(struct amdgpu_device *adev) in cz_process_firmware_header() argument
384 struct cz_power_info *pi = cz_get_pi(adev); in cz_process_firmware_header()
388 ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION + in cz_process_firmware_header()
399 static int cz_dpm_init(struct amdgpu_device *adev) in cz_dpm_init() argument
408 adev->pm.dpm.priv = pi; in cz_dpm_init()
410 ret = amdgpu_get_platform_caps(adev); in cz_dpm_init()
414 ret = amdgpu_parse_extended_power_table(adev); in cz_dpm_init()
448 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; in cz_dpm_init()
451 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; in cz_dpm_init()
454 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; in cz_dpm_init()
464 ret = cz_parse_sys_info_table(adev); in cz_dpm_init()
468 cz_patch_voltage_values(adev); in cz_dpm_init()
469 cz_construct_boot_state(adev); in cz_dpm_init()
471 ret = cz_parse_power_table(adev); in cz_dpm_init()
475 ret = cz_process_firmware_header(adev); in cz_dpm_init()
485 static void cz_dpm_fini(struct amdgpu_device *adev) in cz_dpm_fini() argument
489 for (i = 0; i < adev->pm.dpm.num_ps; i++) in cz_dpm_fini()
490 kfree(adev->pm.dpm.ps[i].ps_priv); in cz_dpm_fini()
492 kfree(adev->pm.dpm.ps); in cz_dpm_fini()
493 kfree(adev->pm.dpm.priv); in cz_dpm_fini()
494 amdgpu_free_extended_power_table(adev); in cz_dpm_fini()
505 cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in cz_dpm_debugfs_print_current_performance_level() argument
508 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_debugfs_print_current_performance_level()
510 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_dpm_debugfs_print_current_performance_level()
512 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_dpm_debugfs_print_current_performance_level()
514 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_dpm_debugfs_print_current_performance_level()
533 vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); in cz_dpm_debugfs_print_current_performance_level()
536 vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp); in cz_dpm_debugfs_print_current_performance_level()
561 static void cz_dpm_print_power_state(struct amdgpu_device *adev, in cz_dpm_print_power_state() argument
576 cz_convert_8bit_index_to_voltage(adev, pl->vddc_index)); in cz_dpm_print_power_state()
579 amdgpu_dpm_print_ps_status(adev, rps); in cz_dpm_print_power_state()
582 static void cz_dpm_set_funcs(struct amdgpu_device *adev);
586 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_early_init() local
588 cz_dpm_set_funcs(adev); in cz_dpm_early_init()
596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_late_init() local
601 ret = amdgpu_pm_sysfs_init(adev); in cz_dpm_late_init()
606 cz_dpm_powergate_uvd(adev, true); in cz_dpm_late_init()
607 cz_dpm_powergate_vce(adev, true); in cz_dpm_late_init()
615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_sw_init() local
620 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in cz_dpm_sw_init()
621 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in cz_dpm_sw_init()
622 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; in cz_dpm_sw_init()
623 adev->pm.default_sclk = adev->clock.default_sclk; in cz_dpm_sw_init()
624 adev->pm.default_mclk = adev->clock.default_mclk; in cz_dpm_sw_init()
625 adev->pm.current_sclk = adev->clock.default_sclk; in cz_dpm_sw_init()
626 adev->pm.current_mclk = adev->clock.default_mclk; in cz_dpm_sw_init()
627 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in cz_dpm_sw_init()
632 mutex_lock(&adev->pm.mutex); in cz_dpm_sw_init()
633 ret = cz_dpm_init(adev); in cz_dpm_sw_init()
637 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in cz_dpm_sw_init()
639 amdgpu_pm_print_power_states(adev); in cz_dpm_sw_init()
641 mutex_unlock(&adev->pm.mutex); in cz_dpm_sw_init()
647 cz_dpm_fini(adev); in cz_dpm_sw_init()
648 mutex_unlock(&adev->pm.mutex); in cz_dpm_sw_init()
656 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_sw_fini() local
658 mutex_lock(&adev->pm.mutex); in cz_dpm_sw_fini()
659 amdgpu_pm_sysfs_fini(adev); in cz_dpm_sw_fini()
660 cz_dpm_fini(adev); in cz_dpm_sw_fini()
661 mutex_unlock(&adev->pm.mutex); in cz_dpm_sw_fini()
666 static void cz_reset_ap_mask(struct amdgpu_device *adev) in cz_reset_ap_mask() argument
668 struct cz_power_info *pi = cz_get_pi(adev); in cz_reset_ap_mask()
674 static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev, in cz_dpm_download_pptable_from_smu() argument
679 ret = cz_smu_download_pptable(adev, table); in cz_dpm_download_pptable_from_smu()
684 static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev) in cz_dpm_upload_pptable_to_smu() argument
686 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_upload_pptable_to_smu()
694 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_dpm_upload_pptable_to_smu()
696 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk; in cz_dpm_upload_pptable_to_smu()
698 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_dpm_upload_pptable_to_smu()
700 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_dpm_upload_pptable_to_smu()
702 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_dpm_upload_pptable_to_smu()
707 ret = cz_dpm_download_pptable_from_smu(adev, &table); in cz_dpm_upload_pptable_to_smu()
731 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, in cz_dpm_upload_pptable_to_smu()
748 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, in cz_dpm_upload_pptable_to_smu()
761 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, in cz_dpm_upload_pptable_to_smu()
773 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, in cz_dpm_upload_pptable_to_smu()
786 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, in cz_dpm_upload_pptable_to_smu()
796 ret = cz_smu_upload_pptable(adev); in cz_dpm_upload_pptable_to_smu()
805 static void cz_init_sclk_limit(struct amdgpu_device *adev) in cz_init_sclk_limit() argument
807 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_sclk_limit()
809 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_init_sclk_limit()
819 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel); in cz_init_sclk_limit()
820 level = cz_get_argument(adev); in cz_init_sclk_limit()
833 static void cz_init_uvd_limit(struct amdgpu_device *adev) in cz_init_uvd_limit() argument
835 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_uvd_limit()
837 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_init_uvd_limit()
847 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel); in cz_init_uvd_limit()
848 level = cz_get_argument(adev); in cz_init_uvd_limit()
861 static void cz_init_vce_limit(struct amdgpu_device *adev) in cz_init_vce_limit() argument
863 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_vce_limit()
865 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_init_vce_limit()
875 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel); in cz_init_vce_limit()
876 level = cz_get_argument(adev); in cz_init_vce_limit()
890 static void cz_init_acp_limit(struct amdgpu_device *adev) in cz_init_acp_limit() argument
892 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_acp_limit()
894 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_init_acp_limit()
904 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel); in cz_init_acp_limit()
905 level = cz_get_argument(adev); in cz_init_acp_limit()
918 static void cz_init_pg_state(struct amdgpu_device *adev) in cz_init_pg_state() argument
920 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_pg_state()
928 static void cz_init_sclk_threshold(struct amdgpu_device *adev) in cz_init_sclk_threshold() argument
930 struct cz_power_info *pi = cz_get_pi(adev); in cz_init_sclk_threshold()
936 static void cz_dpm_setup_asic(struct amdgpu_device *adev) in cz_dpm_setup_asic() argument
938 cz_reset_ap_mask(adev); in cz_dpm_setup_asic()
939 cz_dpm_upload_pptable_to_smu(adev); in cz_dpm_setup_asic()
940 cz_init_sclk_limit(adev); in cz_dpm_setup_asic()
941 cz_init_uvd_limit(adev); in cz_dpm_setup_asic()
942 cz_init_vce_limit(adev); in cz_dpm_setup_asic()
943 cz_init_acp_limit(adev); in cz_dpm_setup_asic()
944 cz_init_pg_state(adev); in cz_dpm_setup_asic()
945 cz_init_sclk_threshold(adev); in cz_dpm_setup_asic()
949 static bool cz_check_smu_feature(struct amdgpu_device *adev, in cz_check_smu_feature() argument
955 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_check_smu_feature()
961 smu_feature = cz_get_argument(adev); in cz_check_smu_feature()
969 static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev) in cz_check_for_dpm_enabled() argument
971 if (cz_check_smu_feature(adev, in cz_check_for_dpm_enabled()
978 static void cz_program_voting_clients(struct amdgpu_device *adev) in cz_program_voting_clients() argument
983 static void cz_clear_voting_clients(struct amdgpu_device *adev) in cz_clear_voting_clients() argument
988 static int cz_start_dpm(struct amdgpu_device *adev) in cz_start_dpm() argument
993 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_start_dpm()
1004 static int cz_stop_dpm(struct amdgpu_device *adev) in cz_stop_dpm() argument
1008 if (amdgpu_dpm && adev->pm.dpm_enabled) { in cz_stop_dpm()
1009 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_stop_dpm()
1020 static uint32_t cz_get_sclk_level(struct amdgpu_device *adev, in cz_get_sclk_level() argument
1025 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_get_sclk_level()
1051 static uint32_t cz_get_eclk_level(struct amdgpu_device *adev, in cz_get_eclk_level() argument
1056 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_get_eclk_level()
1081 static int cz_program_bootup_state(struct amdgpu_device *adev) in cz_program_bootup_state() argument
1083 struct cz_power_info *pi = cz_get_pi(adev); in cz_program_bootup_state()
1091 soft_min_clk = cz_get_sclk_level(adev, in cz_program_bootup_state()
1094 soft_max_clk = cz_get_sclk_level(adev, in cz_program_bootup_state()
1098 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_program_bootup_state()
1103 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_program_bootup_state()
1112 static int cz_disable_cgpg(struct amdgpu_device *adev) in cz_disable_cgpg() argument
1118 static int cz_enable_cgpg(struct amdgpu_device *adev) in cz_enable_cgpg() argument
1124 static int cz_program_pt_config_registers(struct amdgpu_device *adev) in cz_program_pt_config_registers() argument
1129 static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable) in cz_do_enable_didt() argument
1131 struct cz_power_info *pi = cz_get_pi(adev); in cz_do_enable_didt()
1169 static int cz_enable_didt(struct amdgpu_device *adev, bool enable) in cz_enable_didt() argument
1171 struct cz_power_info *pi = cz_get_pi(adev); in cz_enable_didt()
1176 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) { in cz_enable_didt()
1177 ret = cz_disable_cgpg(adev); in cz_enable_didt()
1182 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE; in cz_enable_didt()
1185 ret = cz_program_pt_config_registers(adev); in cz_enable_didt()
1190 cz_do_enable_didt(adev, enable); in cz_enable_didt()
1192 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) { in cz_enable_didt()
1193 ret = cz_enable_cgpg(adev); in cz_enable_didt()
1198 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in cz_enable_didt()
1206 static void cz_reset_acp_boot_level(struct amdgpu_device *adev) in cz_reset_acp_boot_level() argument
1210 static void cz_update_current_ps(struct amdgpu_device *adev, in cz_update_current_ps() argument
1213 struct cz_power_info *pi = cz_get_pi(adev); in cz_update_current_ps()
1222 static void cz_update_requested_ps(struct amdgpu_device *adev, in cz_update_requested_ps() argument
1225 struct cz_power_info *pi = cz_get_pi(adev); in cz_update_requested_ps()
1235 static void cz_apply_state_adjust_rules(struct amdgpu_device *adev, in cz_apply_state_adjust_rules() argument
1240 struct cz_power_info *pi = cz_get_pi(adev); in cz_apply_state_adjust_rules()
1242 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in cz_apply_state_adjust_rules()
1265 static int cz_dpm_enable(struct amdgpu_device *adev) in cz_dpm_enable() argument
1271 if (cz_check_for_dpm_enabled(adev)) in cz_dpm_enable()
1274 cz_program_voting_clients(adev); in cz_dpm_enable()
1276 switch (adev->asic_type) { in cz_dpm_enable()
1288 ret = cz_start_dpm(adev); in cz_dpm_enable()
1294 ret = cz_program_bootup_state(adev); in cz_dpm_enable()
1300 ret = cz_enable_didt(adev, true); in cz_dpm_enable()
1306 cz_reset_acp_boot_level(adev); in cz_dpm_enable()
1308 cz_update_current_ps(adev, adev->pm.dpm.boot_ps); in cz_dpm_enable()
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_hw_init() local
1318 mutex_lock(&adev->pm.mutex); in cz_dpm_hw_init()
1324 ret = cz_smu_init(adev); in cz_dpm_hw_init()
1327 mutex_unlock(&adev->pm.mutex); in cz_dpm_hw_init()
1332 ret = cz_smu_start(adev); in cz_dpm_hw_init()
1335 mutex_unlock(&adev->pm.mutex); in cz_dpm_hw_init()
1340 adev->pm.dpm_enabled = false; in cz_dpm_hw_init()
1341 mutex_unlock(&adev->pm.mutex); in cz_dpm_hw_init()
1346 cz_dpm_setup_asic(adev); in cz_dpm_hw_init()
1349 ret = cz_dpm_enable(adev); in cz_dpm_hw_init()
1351 adev->pm.dpm_enabled = false; in cz_dpm_hw_init()
1353 adev->pm.dpm_enabled = true; in cz_dpm_hw_init()
1355 mutex_unlock(&adev->pm.mutex); in cz_dpm_hw_init()
1360 static int cz_dpm_disable(struct amdgpu_device *adev) in cz_dpm_disable() argument
1364 if (!cz_check_for_dpm_enabled(adev)) in cz_dpm_disable()
1367 ret = cz_enable_didt(adev, false); in cz_dpm_disable()
1374 cz_dpm_powergate_uvd(adev, false); in cz_dpm_disable()
1375 cz_dpm_powergate_vce(adev, false); in cz_dpm_disable()
1377 cz_clear_voting_clients(adev); in cz_dpm_disable()
1378 cz_stop_dpm(adev); in cz_dpm_disable()
1379 cz_update_current_ps(adev, adev->pm.dpm.boot_ps); in cz_dpm_disable()
1387 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_hw_fini() local
1389 mutex_lock(&adev->pm.mutex); in cz_dpm_hw_fini()
1395 cz_smu_fini(adev); in cz_dpm_hw_fini()
1397 if (adev->pm.dpm_enabled) { in cz_dpm_hw_fini()
1398 ret = cz_dpm_disable(adev); in cz_dpm_hw_fini()
1400 adev->pm.dpm.current_ps = in cz_dpm_hw_fini()
1401 adev->pm.dpm.requested_ps = in cz_dpm_hw_fini()
1402 adev->pm.dpm.boot_ps; in cz_dpm_hw_fini()
1405 adev->pm.dpm_enabled = false; in cz_dpm_hw_fini()
1407 mutex_unlock(&adev->pm.mutex); in cz_dpm_hw_fini()
1415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_suspend() local
1417 if (adev->pm.dpm_enabled) { in cz_dpm_suspend()
1418 mutex_lock(&adev->pm.mutex); in cz_dpm_suspend()
1420 ret = cz_dpm_disable(adev); in cz_dpm_suspend()
1422 adev->pm.dpm.current_ps = in cz_dpm_suspend()
1423 adev->pm.dpm.requested_ps = in cz_dpm_suspend()
1424 adev->pm.dpm.boot_ps; in cz_dpm_suspend()
1426 mutex_unlock(&adev->pm.mutex); in cz_dpm_suspend()
1435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cz_dpm_resume() local
1437 mutex_lock(&adev->pm.mutex); in cz_dpm_resume()
1440 ret = cz_smu_start(adev); in cz_dpm_resume()
1443 mutex_unlock(&adev->pm.mutex); in cz_dpm_resume()
1448 adev->pm.dpm_enabled = false; in cz_dpm_resume()
1449 mutex_unlock(&adev->pm.mutex); in cz_dpm_resume()
1454 cz_dpm_setup_asic(adev); in cz_dpm_resume()
1457 ret = cz_dpm_enable(adev); in cz_dpm_resume()
1459 adev->pm.dpm_enabled = false; in cz_dpm_resume()
1461 adev->pm.dpm_enabled = true; in cz_dpm_resume()
1463 mutex_unlock(&adev->pm.mutex); in cz_dpm_resume()
1465 if (adev->pm.dpm_enabled) in cz_dpm_resume()
1466 amdgpu_pm_compute_clocks(adev); in cz_dpm_resume()
1484 static int cz_dpm_get_temperature(struct amdgpu_device *adev) in cz_dpm_get_temperature() argument
1495 static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev) in cz_dpm_pre_set_power_state() argument
1497 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_pre_set_power_state()
1498 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in cz_dpm_pre_set_power_state()
1501 cz_update_requested_ps(adev, new_ps); in cz_dpm_pre_set_power_state()
1502 cz_apply_state_adjust_rules(adev, &pi->requested_rps, in cz_dpm_pre_set_power_state()
1508 static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev) in cz_dpm_update_sclk_limit() argument
1510 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_update_sclk_limit()
1512 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in cz_dpm_update_sclk_limit()
1525 cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_update_sclk_limit()
1527 cz_get_sclk_level(adev, clock, in cz_dpm_update_sclk_limit()
1534 cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_update_sclk_limit()
1536 cz_get_sclk_level(adev, clock, in cz_dpm_update_sclk_limit()
1539 cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_update_sclk_limit()
1541 cz_get_sclk_level(adev, in cz_dpm_update_sclk_limit()
1549 static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev) in cz_dpm_set_deep_sleep_sclk_threshold() argument
1552 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_set_deep_sleep_sclk_threshold()
1555 cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_set_deep_sleep_sclk_threshold()
1564 static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev) in cz_dpm_set_watermark_threshold() argument
1567 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_set_watermark_threshold()
1569 cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_set_watermark_threshold()
1576 static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev) in cz_dpm_enable_nbdpm() argument
1579 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_enable_nbdpm()
1583 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_enable_nbdpm()
1596 static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev, in cz_dpm_nbdpm_lm_pstate_enable() argument
1600 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate); in cz_dpm_nbdpm_lm_pstate_enable()
1602 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate); in cz_dpm_nbdpm_lm_pstate_enable()
1606 static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev) in cz_dpm_update_low_memory_pstate() argument
1609 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_update_low_memory_pstate()
1614 cz_dpm_nbdpm_lm_pstate_enable(adev, false); in cz_dpm_update_low_memory_pstate()
1616 cz_dpm_nbdpm_lm_pstate_enable(adev, true); in cz_dpm_update_low_memory_pstate()
1623 static int cz_dpm_set_power_state(struct amdgpu_device *adev) in cz_dpm_set_power_state() argument
1627 cz_dpm_update_sclk_limit(adev); in cz_dpm_set_power_state()
1628 cz_dpm_set_deep_sleep_sclk_threshold(adev); in cz_dpm_set_power_state()
1629 cz_dpm_set_watermark_threshold(adev); in cz_dpm_set_power_state()
1630 cz_dpm_enable_nbdpm(adev); in cz_dpm_set_power_state()
1631 cz_dpm_update_low_memory_pstate(adev); in cz_dpm_set_power_state()
1636 static void cz_dpm_post_set_power_state(struct amdgpu_device *adev) in cz_dpm_post_set_power_state() argument
1638 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_post_set_power_state()
1641 cz_update_current_ps(adev, ps); in cz_dpm_post_set_power_state()
1645 static int cz_dpm_force_highest(struct amdgpu_device *adev) in cz_dpm_force_highest() argument
1647 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_force_highest()
1653 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_force_highest()
1655 cz_get_sclk_level(adev, in cz_dpm_force_highest()
1665 static int cz_dpm_force_lowest(struct amdgpu_device *adev) in cz_dpm_force_lowest() argument
1667 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_force_lowest()
1672 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_force_lowest()
1674 cz_get_sclk_level(adev, in cz_dpm_force_lowest()
1684 static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev) in cz_dpm_get_max_sclk_level() argument
1686 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_get_max_sclk_level()
1689 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel); in cz_dpm_get_max_sclk_level()
1690 pi->max_sclk_level = cz_get_argument(adev) + 1; in cz_dpm_get_max_sclk_level()
1701 static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev) in cz_dpm_unforce_dpm_levels() argument
1703 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_unforce_dpm_levels()
1705 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_dpm_unforce_dpm_levels()
1710 level = cz_dpm_get_max_sclk_level(adev) - 1; in cz_dpm_unforce_dpm_levels()
1719 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_unforce_dpm_levels()
1721 cz_get_sclk_level(adev, in cz_dpm_unforce_dpm_levels()
1727 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_dpm_unforce_dpm_levels()
1729 cz_get_sclk_level(adev, in cz_dpm_unforce_dpm_levels()
1742 static int cz_dpm_force_dpm_level(struct amdgpu_device *adev, in cz_dpm_force_dpm_level() argument
1749 ret = cz_dpm_unforce_dpm_levels(adev); in cz_dpm_force_dpm_level()
1752 ret = cz_dpm_force_highest(adev); in cz_dpm_force_dpm_level()
1757 ret = cz_dpm_unforce_dpm_levels(adev); in cz_dpm_force_dpm_level()
1760 ret = cz_dpm_force_lowest(adev); in cz_dpm_force_dpm_level()
1765 ret = cz_dpm_unforce_dpm_levels(adev); in cz_dpm_force_dpm_level()
1773 adev->pm.dpm.forced_level = level; in cz_dpm_force_dpm_level()
1780 static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev) in cz_dpm_display_configuration_changed() argument
1784 static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low) in cz_dpm_get_sclk() argument
1786 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_get_sclk()
1796 static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low) in cz_dpm_get_mclk() argument
1798 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_get_mclk()
1803 static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) in cz_enable_uvd_dpm() argument
1805 struct cz_power_info *pi = cz_get_pi(adev); in cz_enable_uvd_dpm()
1812 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_enable_uvd_dpm()
1818 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_enable_uvd_dpm()
1825 static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in cz_update_uvd_dpm() argument
1827 return cz_enable_uvd_dpm(adev, !gate); in cz_update_uvd_dpm()
1831 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) in cz_dpm_powergate_uvd() argument
1833 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_powergate_uvd()
1844 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in cz_dpm_powergate_uvd()
1847 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in cz_dpm_powergate_uvd()
1851 cz_update_uvd_dpm(adev, gate); in cz_dpm_powergate_uvd()
1854 cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF); in cz_dpm_powergate_uvd()
1859 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1); in cz_dpm_powergate_uvd()
1861 cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0); in cz_dpm_powergate_uvd()
1863 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in cz_dpm_powergate_uvd()
1866 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in cz_dpm_powergate_uvd()
1870 cz_update_uvd_dpm(adev, gate); in cz_dpm_powergate_uvd()
1874 static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable) in cz_enable_vce_dpm() argument
1876 struct cz_power_info *pi = cz_get_pi(adev); in cz_enable_vce_dpm()
1883 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_enable_vce_dpm()
1890 ret = cz_send_msg_to_smc_with_parameter(adev, in cz_enable_vce_dpm()
1897 static int cz_update_vce_dpm(struct amdgpu_device *adev) in cz_update_vce_dpm() argument
1899 struct cz_power_info *pi = cz_get_pi(adev); in cz_update_vce_dpm()
1901 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_update_vce_dpm()
1911 cz_send_msg_to_smc_with_parameter(adev, in cz_update_vce_dpm()
1913 cz_get_eclk_level(adev, in cz_update_vce_dpm()
1919 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) in cz_dpm_powergate_vce() argument
1921 struct cz_power_info *pi = cz_get_pi(adev); in cz_dpm_powergate_vce()
1927 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in cz_dpm_powergate_vce()
1930 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in cz_dpm_powergate_vce()
1933 cz_enable_vce_dpm(adev, false); in cz_dpm_powergate_vce()
1938 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON); in cz_dpm_powergate_vce()
1942 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in cz_dpm_powergate_vce()
1945 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in cz_dpm_powergate_vce()
1948 cz_update_vce_dpm(adev); in cz_dpm_powergate_vce()
1949 cz_enable_vce_dpm(adev, true); in cz_dpm_powergate_vce()
1953 cz_update_vce_dpm(adev); in cz_dpm_powergate_vce()
1957 cz_update_vce_dpm(adev); in cz_dpm_powergate_vce()
1958 cz_enable_vce_dpm(adev, true); in cz_dpm_powergate_vce()
1998 static void cz_dpm_set_funcs(struct amdgpu_device *adev) in cz_dpm_set_funcs() argument
2000 if (NULL == adev->pm.funcs) in cz_dpm_set_funcs()
2001 adev->pm.funcs = &cz_dpm_funcs; in cz_dpm_set_funcs()