188 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);  in cik_sdma_ring_set_wptr()
342 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_stop()
343 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_stop()
385 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);  in cik_sdma_enable()
413 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
414 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
420 		WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
421 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
430 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_resume()
433 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
434 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
437 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],  in cik_sdma_gfx_resume()
439 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],  in cik_sdma_gfx_resume()
444 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in cik_sdma_gfx_resume()
445 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in cik_sdma_gfx_resume()
448 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);  in cik_sdma_gfx_resume()
451 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],  in cik_sdma_gfx_resume()
459 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in cik_sdma_gfx_resume()
520 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);  in cik_sdma_load_microcode()
522 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
523 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in cik_sdma_load_microcode()
889 		WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);  in cik_enable_sdma_mgcg()
890 		WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);  in cik_enable_sdma_mgcg()
895 			WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgcg()
900 			WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);  in cik_enable_sdma_mgcg()
913 			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
918 			WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
923 			WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
928 			WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
1124 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_sdma_soft_reset()
1131 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_sdma_soft_reset()
1141 		WREG32(mmSRBM_SOFT_RESET, tmp);  in cik_sdma_soft_reset()
1147 		WREG32(mmSRBM_SOFT_RESET, tmp);  in cik_sdma_soft_reset()
1172 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);  in cik_sdma_set_trap_irq_state()
1177 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);  in cik_sdma_set_trap_irq_state()
1188 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);  in cik_sdma_set_trap_irq_state()
1193 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);  in cik_sdma_set_trap_irq_state()