49 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev);
58 static void cik_ih_enable_interrupts(struct amdgpu_device *adev)  in cik_ih_enable_interrupts()  argument
67 	adev->irq.ih.enabled = true;  in cik_ih_enable_interrupts()
77 static void cik_ih_disable_interrupts(struct amdgpu_device *adev)  in cik_ih_disable_interrupts()  argument
89 	adev->irq.ih.enabled = false;  in cik_ih_disable_interrupts()
90 	adev->irq.ih.rptr = 0;  in cik_ih_disable_interrupts()
104 static int cik_ih_irq_init(struct amdgpu_device *adev)  in cik_ih_irq_init()  argument
112 	cik_ih_disable_interrupts(adev);  in cik_ih_irq_init()
115 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);  in cik_ih_irq_init()
125 	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in cik_ih_irq_init()
126 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in cik_ih_irq_init()
135 	wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);  in cik_ih_irq_init()
150 	if (adev->irq.msi_enabled)  in cik_ih_irq_init()
154 	pci_set_master(adev->pdev);  in cik_ih_irq_init()
157 	cik_ih_enable_interrupts(adev);  in cik_ih_irq_init()
169 static void cik_ih_irq_disable(struct amdgpu_device *adev)  in cik_ih_irq_disable()  argument
171 	cik_ih_disable_interrupts(adev);  in cik_ih_irq_disable()
187 static u32 cik_ih_get_wptr(struct amdgpu_device *adev)  in cik_ih_get_wptr()  argument
191 	wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);  in cik_ih_get_wptr()
199 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in cik_ih_get_wptr()
200 			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);  in cik_ih_get_wptr()
201 		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;  in cik_ih_get_wptr()
206 	return (wptr & adev->irq.ih.ptr_mask);  in cik_ih_get_wptr()
240 static void cik_ih_decode_iv(struct amdgpu_device *adev,  in cik_ih_decode_iv()  argument
244 	u32 ring_index = adev->irq.ih.rptr >> 2;  in cik_ih_decode_iv()
247 	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);  in cik_ih_decode_iv()
248 	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);  in cik_ih_decode_iv()
249 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);  in cik_ih_decode_iv()
250 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);  in cik_ih_decode_iv()
259 	adev->irq.ih.rptr += 16;  in cik_ih_decode_iv()
269 static void cik_ih_set_rptr(struct amdgpu_device *adev)  in cik_ih_set_rptr()  argument
271 	WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);  in cik_ih_set_rptr()
276 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_early_init()  local
278 	cik_ih_set_interrupt_funcs(adev);  in cik_ih_early_init()
286 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_sw_init()  local
288 	r = amdgpu_ih_ring_init(adev, 64 * 1024, false);  in cik_ih_sw_init()
292 	r = amdgpu_irq_init(adev);  in cik_ih_sw_init()
299 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_sw_fini()  local
301 	amdgpu_irq_fini(adev);  in cik_ih_sw_fini()
302 	amdgpu_ih_ring_fini(adev);  in cik_ih_sw_fini()
310 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_hw_init()  local
312 	r = cik_ih_irq_init(adev);  in cik_ih_hw_init()
321 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_hw_fini()  local
323 	cik_ih_irq_disable(adev);  in cik_ih_hw_fini()
330 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_suspend()  local
332 	return cik_ih_hw_fini(adev);  in cik_ih_suspend()
337 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_resume()  local
339 	return cik_ih_hw_init(adev);  in cik_ih_resume()
344 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_is_idle()  local
357 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_wait_for_idle()  local
359 	for (i = 0; i < adev->usec_timeout; i++) {  in cik_ih_wait_for_idle()
371 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_print_status()  local
373 	dev_info(adev->dev, "CIK IH registers\n");  in cik_ih_print_status()
374 	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",  in cik_ih_print_status()
376 	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",  in cik_ih_print_status()
378 	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",  in cik_ih_print_status()
380 	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",  in cik_ih_print_status()
382 	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",  in cik_ih_print_status()
384 	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",  in cik_ih_print_status()
386 	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",  in cik_ih_print_status()
388 	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",  in cik_ih_print_status()
390 	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",  in cik_ih_print_status()
392 	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",  in cik_ih_print_status()
394 	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",  in cik_ih_print_status()
400 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in cik_ih_soft_reset()  local
409 		cik_ih_print_status((void *)adev);  in cik_ih_soft_reset()
413 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in cik_ih_soft_reset()
426 		cik_ih_print_status((void *)adev);  in cik_ih_soft_reset()
467 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev)  in cik_ih_set_interrupt_funcs()  argument
469 	if (adev->irq.ih_funcs == NULL)  in cik_ih_set_interrupt_funcs()
470 		adev->irq.ih_funcs = &cik_ih_funcs;  in cik_ih_set_interrupt_funcs()