Lines Matching refs:WREG32
65 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_enable_interrupts()
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_enable_interrupts()
84 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_disable_interrupts()
85 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_disable_interrupts()
87 WREG32(mmIH_RB_RPTR, 0); in cik_ih_disable_interrupts()
88 WREG32(mmIH_RB_WPTR, 0); in cik_ih_disable_interrupts()
115 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); in cik_ih_irq_init()
123 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); in cik_ih_irq_init()
125 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); in cik_ih_irq_init()
139 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_irq_init()
142 WREG32(mmIH_RB_RPTR, 0); in cik_ih_irq_init()
143 WREG32(mmIH_RB_WPTR, 0); in cik_ih_irq_init()
152 WREG32(mmIH_CNTL, ih_cntl); in cik_ih_irq_init()
204 WREG32(mmIH_RB_CNTL, tmp); in cik_ih_get_wptr()
271 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); in cik_ih_set_rptr()
414 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_ih_soft_reset()
420 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_ih_soft_reset()