877 	uint32_t tmp;  in cik_vga_set_state()  local
879 	tmp = RREG32(mmCONFIG_CNTL);  in cik_vga_set_state()
881 		tmp |= CONFIG_CNTL__VGA_DIS_MASK;  in cik_vga_set_state()
883 		tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;  in cik_vga_set_state()
884 	WREG32(mmCONFIG_CNTL, tmp);  in cik_vga_set_state()
1081 	u32 tmp;  in amdgpu_cik_gpu_check_soft_reset()  local
1084 	tmp = RREG32(mmGRBM_STATUS);  in amdgpu_cik_gpu_check_soft_reset()
1085 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |  in amdgpu_cik_gpu_check_soft_reset()
1093 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))  in amdgpu_cik_gpu_check_soft_reset()
1097 	tmp = RREG32(mmGRBM_STATUS2);  in amdgpu_cik_gpu_check_soft_reset()
1098 	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1102 	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);  in amdgpu_cik_gpu_check_soft_reset()
1103 	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))  in amdgpu_cik_gpu_check_soft_reset()
1107 	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);  in amdgpu_cik_gpu_check_soft_reset()
1108 	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))  in amdgpu_cik_gpu_check_soft_reset()
1112 	tmp = RREG32(mmSRBM_STATUS2);  in amdgpu_cik_gpu_check_soft_reset()
1113 	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1116 	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1120 	tmp = RREG32(mmSRBM_STATUS);  in amdgpu_cik_gpu_check_soft_reset()
1122 	if (tmp & SRBM_STATUS__IH_BUSY_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1125 	if (tmp & SRBM_STATUS__SEM_BUSY_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1128 	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1131 	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)  in amdgpu_cik_gpu_check_soft_reset()
1134 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in amdgpu_cik_gpu_check_soft_reset()
1162 	u32 tmp;  in cik_gpu_soft_reset()  local
1188 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_soft_reset()
1189 		tmp |= SDMA0_F32_CNTL__HALT_MASK;  in cik_gpu_soft_reset()
1190 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
1194 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in cik_gpu_soft_reset()
1195 		tmp |= SDMA0_F32_CNTL__HALT_MASK;  in cik_gpu_soft_reset()
1196 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
1244 		tmp = RREG32(mmGRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1245 		tmp |= grbm_soft_reset;  in cik_gpu_soft_reset()
1246 		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in cik_gpu_soft_reset()
1247 		WREG32(mmGRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1248 		tmp = RREG32(mmGRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1252 		tmp &= ~grbm_soft_reset;  in cik_gpu_soft_reset()
1253 		WREG32(mmGRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1254 		tmp = RREG32(mmGRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1258 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1259 		tmp |= srbm_soft_reset;  in cik_gpu_soft_reset()
1260 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in cik_gpu_soft_reset()
1261 		WREG32(mmSRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1262 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1266 		tmp &= ~srbm_soft_reset;  in cik_gpu_soft_reset()
1267 		WREG32(mmSRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1268 		tmp = RREG32(mmSRBM_SOFT_RESET);  in cik_gpu_soft_reset()
1377 	u32 tmp, i;  in cik_gpu_pci_config_reset()  local
1394 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
1395 	tmp |= SDMA0_F32_CNTL__HALT_MASK;  in cik_gpu_pci_config_reset()
1396 	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
1398 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
1399 	tmp |= SDMA0_F32_CNTL__HALT_MASK;  in cik_gpu_pci_config_reset()
1400 	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
1438 	u32 tmp = RREG32(mmBIOS_SCRATCH_3);  in cik_set_bios_scratch_engine_hung()  local
1441 		tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;  in cik_set_bios_scratch_engine_hung()
1443 		tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;  in cik_set_bios_scratch_engine_hung()
1445 	WREG32(mmBIOS_SCRATCH_3, tmp);  in cik_set_bios_scratch_engine_hung()
1488 	uint32_t tmp;  in cik_set_uvd_clock()  local
1496 	tmp = RREG32_SMC(cntl_reg);  in cik_set_uvd_clock()
1497 	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |  in cik_set_uvd_clock()
1499 	tmp |= dividers.post_divider;  in cik_set_uvd_clock()
1500 	WREG32_SMC(cntl_reg, tmp);  in cik_set_uvd_clock()
1529 	u32 tmp;  in cik_set_vce_clocks()  local
1545 	tmp = RREG32_SMC(ixCG_ECLK_CNTL);  in cik_set_vce_clocks()
1546 	tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |  in cik_set_vce_clocks()
1548 	tmp |= dividers.post_divider;  in cik_set_vce_clocks()
1549 	WREG32_SMC(ixCG_ECLK_CNTL, tmp);  in cik_set_vce_clocks()
1616 			u32 max_lw, current_lw, tmp;  in cik_pcie_gen3_enable()  local
1627 			tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);  in cik_pcie_gen3_enable()
1628 			max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>  in cik_pcie_gen3_enable()
1630 			current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)  in cik_pcie_gen3_enable()
1634 				tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);  in cik_pcie_gen3_enable()
1635 				if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {  in cik_pcie_gen3_enable()
1636 					tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |  in cik_pcie_gen3_enable()
1638 					tmp |= (max_lw <<  in cik_pcie_gen3_enable()
1640 					tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |  in cik_pcie_gen3_enable()
1643 					WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);  in cik_pcie_gen3_enable()
1659 				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);  in cik_pcie_gen3_enable()
1660 				tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;  in cik_pcie_gen3_enable()
1661 				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);  in cik_pcie_gen3_enable()
1663 				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);  in cik_pcie_gen3_enable()
1664 				tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;  in cik_pcie_gen3_enable()
1665 				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);  in cik_pcie_gen3_enable()
1691 				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);  in cik_pcie_gen3_enable()
1692 				tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;  in cik_pcie_gen3_enable()
1693 				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);  in cik_pcie_gen3_enable()