Lines Matching refs:adev
72 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) in cik_pcie_rreg() argument
77 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
81 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_rreg()
85 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_pcie_wreg() argument
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in cik_pcie_wreg()
97 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) in cik_smc_rreg() argument
102 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cik_smc_rreg()
105 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cik_smc_rreg()
109 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_smc_wreg() argument
113 spin_lock_irqsave(&adev->smc_idx_lock, flags); in cik_smc_wreg()
116 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in cik_smc_wreg()
119 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in cik_uvd_ctx_rreg() argument
124 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in cik_uvd_ctx_rreg()
127 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in cik_uvd_ctx_rreg()
131 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_uvd_ctx_wreg() argument
135 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in cik_uvd_ctx_wreg()
138 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in cik_uvd_ctx_wreg()
141 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) in cik_didt_rreg() argument
146 spin_lock_irqsave(&adev->didt_idx_lock, flags); in cik_didt_rreg()
149 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in cik_didt_rreg()
153 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in cik_didt_wreg() argument
157 spin_lock_irqsave(&adev->didt_idx_lock, flags); in cik_didt_wreg()
160 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in cik_didt_wreg()
747 static void cik_init_golden_registers(struct amdgpu_device *adev) in cik_init_golden_registers() argument
750 mutex_lock(&adev->grbm_idx_mutex); in cik_init_golden_registers()
752 switch (adev->asic_type) { in cik_init_golden_registers()
754 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
757 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
760 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
763 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
768 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
771 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
774 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
777 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
782 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
785 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
788 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
791 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
796 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
799 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
802 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
805 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
810 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
813 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
816 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
819 amdgpu_program_register_sequence(adev, in cik_init_golden_registers()
826 mutex_unlock(&adev->grbm_idx_mutex); in cik_init_golden_registers()
837 static u32 cik_get_xclk(struct amdgpu_device *adev) in cik_get_xclk() argument
839 u32 reference_clock = adev->clock.spll.reference_freq; in cik_get_xclk()
841 if (adev->flags & AMD_IS_APU) { in cik_get_xclk()
864 void cik_srbm_select(struct amdgpu_device *adev, in cik_srbm_select() argument
875 static void cik_vga_set_state(struct amdgpu_device *adev, bool state) in cik_vga_set_state() argument
887 static bool cik_read_disabled_bios(struct amdgpu_device *adev) in cik_read_disabled_bios() argument
897 if (adev->mode_info.num_crtc) { in cik_read_disabled_bios()
906 if (adev->mode_info.num_crtc) { in cik_read_disabled_bios()
919 r = amdgpu_read_bios(adev); in cik_read_disabled_bios()
923 if (adev->mode_info.num_crtc) { in cik_read_disabled_bios()
991 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev, in cik_read_indexed_register() argument
997 mutex_lock(&adev->grbm_idx_mutex); in cik_read_indexed_register()
999 gfx_v7_0_select_se_sh(adev, se_num, sh_num); in cik_read_indexed_register()
1004 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); in cik_read_indexed_register()
1005 mutex_unlock(&adev->grbm_idx_mutex); in cik_read_indexed_register()
1009 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, in cik_read_register() argument
1021 cik_read_indexed_register(adev, se_num, in cik_read_register()
1029 static void cik_print_gpu_status_regs(struct amdgpu_device *adev) in cik_print_gpu_status_regs() argument
1031 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", in cik_print_gpu_status_regs()
1033 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", in cik_print_gpu_status_regs()
1035 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", in cik_print_gpu_status_regs()
1037 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", in cik_print_gpu_status_regs()
1039 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", in cik_print_gpu_status_regs()
1041 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", in cik_print_gpu_status_regs()
1043 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", in cik_print_gpu_status_regs()
1045 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", in cik_print_gpu_status_regs()
1047 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", in cik_print_gpu_status_regs()
1049 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", in cik_print_gpu_status_regs()
1051 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); in cik_print_gpu_status_regs()
1052 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", in cik_print_gpu_status_regs()
1054 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", in cik_print_gpu_status_regs()
1056 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", in cik_print_gpu_status_regs()
1058 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", in cik_print_gpu_status_regs()
1060 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", in cik_print_gpu_status_regs()
1062 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); in cik_print_gpu_status_regs()
1063 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); in cik_print_gpu_status_regs()
1064 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", in cik_print_gpu_status_regs()
1066 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); in cik_print_gpu_status_regs()
1078 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev) in amdgpu_cik_gpu_check_soft_reset() argument
1138 if (amdgpu_display_is_display_hung(adev)) in amdgpu_cik_gpu_check_soft_reset()
1158 static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) in cik_gpu_soft_reset() argument
1167 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cik_gpu_soft_reset()
1169 cik_print_gpu_status_regs(adev); in cik_gpu_soft_reset()
1170 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cik_gpu_soft_reset()
1172 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cik_gpu_soft_reset()
1178 gfx_v7_0_rlc_stop(adev); in cik_gpu_soft_reset()
1199 gmc_v7_0_mc_stop(adev, &save); in cik_gpu_soft_reset()
1200 if (amdgpu_asic_wait_for_mc_idle(adev)) { in cik_gpu_soft_reset()
1201 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in cik_gpu_soft_reset()
1238 if (!(adev->flags & AMD_IS_APU)) { in cik_gpu_soft_reset()
1246 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cik_gpu_soft_reset()
1260 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cik_gpu_soft_reset()
1274 gmc_v7_0_mc_resume(adev, &save); in cik_gpu_soft_reset()
1277 cik_print_gpu_status_regs(adev); in cik_gpu_soft_reset()
1286 static void kv_save_regs_for_reset(struct amdgpu_device *adev, in kv_save_regs_for_reset() argument
1300 static void kv_restore_regs_for_reset(struct amdgpu_device *adev, in kv_restore_regs_for_reset() argument
1373 static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) in cik_gpu_pci_config_reset() argument
1379 dev_info(adev->dev, "GPU pci config reset\n"); in cik_gpu_pci_config_reset()
1404 gfx_v7_0_rlc_stop(adev); in cik_gpu_pci_config_reset()
1409 gmc_v7_0_mc_stop(adev, &save); in cik_gpu_pci_config_reset()
1410 if (amdgpu_asic_wait_for_mc_idle(adev)) { in cik_gpu_pci_config_reset()
1411 dev_warn(adev->dev, "Wait for MC idle timed out !\n"); in cik_gpu_pci_config_reset()
1414 if (adev->flags & AMD_IS_APU) in cik_gpu_pci_config_reset()
1415 kv_save_regs_for_reset(adev, &kv_save); in cik_gpu_pci_config_reset()
1418 pci_clear_master(adev->pdev); in cik_gpu_pci_config_reset()
1420 amdgpu_pci_config_reset(adev); in cik_gpu_pci_config_reset()
1425 for (i = 0; i < adev->usec_timeout; i++) { in cik_gpu_pci_config_reset()
1432 if (adev->flags & AMD_IS_APU) in cik_gpu_pci_config_reset()
1433 kv_restore_regs_for_reset(adev, &kv_save); in cik_gpu_pci_config_reset()
1436 static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) in cik_set_bios_scratch_engine_hung() argument
1457 static int cik_asic_reset(struct amdgpu_device *adev) in cik_asic_reset() argument
1461 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); in cik_asic_reset()
1464 cik_set_bios_scratch_engine_hung(adev, true); in cik_asic_reset()
1467 cik_gpu_soft_reset(adev, reset_mask); in cik_asic_reset()
1469 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); in cik_asic_reset()
1473 cik_gpu_pci_config_reset(adev); in cik_asic_reset()
1475 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); in cik_asic_reset()
1478 cik_set_bios_scratch_engine_hung(adev, false); in cik_asic_reset()
1483 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, in cik_set_uvd_clock() argument
1490 r = amdgpu_atombios_get_clock_dividers(adev, in cik_set_uvd_clock()
1513 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in cik_set_uvd_clocks() argument
1517 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in cik_set_uvd_clocks()
1521 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in cik_set_uvd_clocks()
1525 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in cik_set_vce_clocks() argument
1531 r = amdgpu_atombios_get_clock_dividers(adev, in cik_set_vce_clocks()
1562 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) in cik_pcie_gen3_enable() argument
1564 struct pci_dev *root = adev->pdev->bus->self; in cik_pcie_gen3_enable()
1570 if (pci_is_root_bus(adev->pdev->bus)) in cik_pcie_gen3_enable()
1576 if (adev->flags & AMD_IS_APU) in cik_pcie_gen3_enable()
1579 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); in cik_pcie_gen3_enable()
1607 gpu_pos = pci_pcie_cap(adev->pdev); in cik_pcie_gen3_enable()
1619 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); in cik_pcie_gen3_enable()
1625 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); in cik_pcie_gen3_enable()
1649 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); in cik_pcie_gen3_enable()
1654 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); in cik_pcie_gen3_enable()
1657 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); in cik_pcie_gen3_enable()
1675 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); in cik_pcie_gen3_enable()
1678 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); in cik_pcie_gen3_enable()
1686 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); in cik_pcie_gen3_enable()
1689 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); in cik_pcie_gen3_enable()
1704 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); in cik_pcie_gen3_enable()
1712 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); in cik_pcie_gen3_enable()
1718 for (i = 0; i < adev->usec_timeout; i++) { in cik_pcie_gen3_enable()
1726 static void cik_program_aspm(struct amdgpu_device *adev) in cik_program_aspm() argument
1736 if (adev->flags & AMD_IS_APU) in cik_program_aspm()
1811 struct pci_dev *root = adev->pdev->bus->self; in cik_program_aspm()
1890 static uint32_t cik_get_rev_id(struct amdgpu_device *adev) in cik_get_rev_id() argument
2236 int cik_set_ip_blocks(struct amdgpu_device *adev) in cik_set_ip_blocks() argument
2238 switch (adev->asic_type) { in cik_set_ip_blocks()
2240 adev->ip_blocks = bonaire_ip_blocks; in cik_set_ip_blocks()
2241 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); in cik_set_ip_blocks()
2244 adev->ip_blocks = hawaii_ip_blocks; in cik_set_ip_blocks()
2245 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); in cik_set_ip_blocks()
2248 adev->ip_blocks = kaveri_ip_blocks; in cik_set_ip_blocks()
2249 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); in cik_set_ip_blocks()
2252 adev->ip_blocks = kabini_ip_blocks; in cik_set_ip_blocks()
2253 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); in cik_set_ip_blocks()
2256 adev->ip_blocks = mullins_ip_blocks; in cik_set_ip_blocks()
2257 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); in cik_set_ip_blocks()
2284 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cik_common_early_init() local
2286 adev->smc_rreg = &cik_smc_rreg; in cik_common_early_init()
2287 adev->smc_wreg = &cik_smc_wreg; in cik_common_early_init()
2288 adev->pcie_rreg = &cik_pcie_rreg; in cik_common_early_init()
2289 adev->pcie_wreg = &cik_pcie_wreg; in cik_common_early_init()
2290 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; in cik_common_early_init()
2291 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; in cik_common_early_init()
2292 adev->didt_rreg = &cik_didt_rreg; in cik_common_early_init()
2293 adev->didt_wreg = &cik_didt_wreg; in cik_common_early_init()
2295 adev->asic_funcs = &cik_asic_funcs; in cik_common_early_init()
2297 adev->has_uvd = true; in cik_common_early_init()
2299 adev->rev_id = cik_get_rev_id(adev); in cik_common_early_init()
2300 adev->external_rev_id = 0xFF; in cik_common_early_init()
2301 switch (adev->asic_type) { in cik_common_early_init()
2303 adev->cg_flags = in cik_common_early_init()
2320 adev->pg_flags = 0; in cik_common_early_init()
2321 adev->external_rev_id = adev->rev_id + 0x14; in cik_common_early_init()
2324 adev->cg_flags = in cik_common_early_init()
2340 adev->pg_flags = 0; in cik_common_early_init()
2341 adev->external_rev_id = 0x28; in cik_common_early_init()
2344 adev->cg_flags = in cik_common_early_init()
2359 adev->pg_flags = in cik_common_early_init()
2371 if (adev->pdev->device == 0x1312 || in cik_common_early_init()
2372 adev->pdev->device == 0x1316 || in cik_common_early_init()
2373 adev->pdev->device == 0x1317) in cik_common_early_init()
2374 adev->external_rev_id = 0x41; in cik_common_early_init()
2376 adev->external_rev_id = 0x1; in cik_common_early_init()
2380 adev->cg_flags = in cik_common_early_init()
2395 adev->pg_flags = in cik_common_early_init()
2405 if (adev->asic_type == CHIP_KABINI) { in cik_common_early_init()
2406 if (adev->rev_id == 0) in cik_common_early_init()
2407 adev->external_rev_id = 0x81; in cik_common_early_init()
2408 else if (adev->rev_id == 1) in cik_common_early_init()
2409 adev->external_rev_id = 0x82; in cik_common_early_init()
2410 else if (adev->rev_id == 2) in cik_common_early_init()
2411 adev->external_rev_id = 0x85; in cik_common_early_init()
2413 adev->external_rev_id = adev->rev_id + 0xa1; in cik_common_early_init()
2435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cik_common_hw_init() local
2438 cik_init_golden_registers(adev); in cik_common_hw_init()
2440 cik_pcie_gen3_enable(adev); in cik_common_hw_init()
2442 cik_program_aspm(adev); in cik_common_hw_init()
2454 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cik_common_suspend() local
2456 amdgpu_amdkfd_suspend(adev); in cik_common_suspend()
2458 return cik_common_hw_fini(adev); in cik_common_suspend()
2464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in cik_common_resume() local
2466 r = cik_common_hw_init(adev); in cik_common_resume()
2470 return amdgpu_amdkfd_resume(adev); in cik_common_resume()