78 	WREG32(mmPCIE_INDEX, reg);  in cik_pcie_rreg()
90 	WREG32(mmPCIE_INDEX, reg);  in cik_pcie_wreg()
92 	WREG32(mmPCIE_DATA, v);  in cik_pcie_wreg()
103 	WREG32(mmSMC_IND_INDEX_0, (reg));  in cik_smc_rreg()
114 	WREG32(mmSMC_IND_INDEX_0, (reg));  in cik_smc_wreg()
115 	WREG32(mmSMC_IND_DATA_0, (v));  in cik_smc_wreg()
125 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));  in cik_uvd_ctx_rreg()
136 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));  in cik_uvd_ctx_wreg()
137 	WREG32(mmUVD_CTX_DATA, (v));  in cik_uvd_ctx_wreg()
147 	WREG32(mmDIDT_IND_INDEX, (reg));  in cik_didt_rreg()
158 	WREG32(mmDIDT_IND_INDEX, (reg));  in cik_didt_wreg()
159 	WREG32(mmDIDT_IND_DATA, (v));  in cik_didt_wreg()
872 	WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);  in cik_srbm_select()
884 	WREG32(mmCONFIG_CNTL, tmp);  in cik_vga_set_state()
905 	WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));  in cik_read_disabled_bios()
908 		WREG32(mmD1VGA_CONTROL,  in cik_read_disabled_bios()
911 		WREG32(mmD2VGA_CONTROL,  in cik_read_disabled_bios()
914 		WREG32(mmVGA_RENDER_CONTROL,  in cik_read_disabled_bios()
922 	WREG32(mmBUS_CNTL, bus_cntl);  in cik_read_disabled_bios()
924 		WREG32(mmD1VGA_CONTROL, d1vga_control);  in cik_read_disabled_bios()
925 		WREG32(mmD2VGA_CONTROL, d2vga_control);  in cik_read_disabled_bios()
926 		WREG32(mmVGA_RENDER_CONTROL, vga_render_control);  in cik_read_disabled_bios()
1181 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA…  in cik_gpu_soft_reset()
1184 	WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);  in cik_gpu_soft_reset()
1190 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
1196 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
1247 		WREG32(mmGRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1253 		WREG32(mmGRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1261 		WREG32(mmSRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1267 		WREG32(mmSRBM_SOFT_RESET, tmp);  in cik_gpu_soft_reset()
1293 	WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &  in kv_save_regs_for_reset()
1295 	WREG32(mmGMCON_MISC, save->gmcon_misc &  in kv_save_regs_for_reset()
1305 	WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1306 	WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);  in kv_restore_regs_for_reset()
1309 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1311 	WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1312 	WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);  in kv_restore_regs_for_reset()
1315 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1317 	WREG32(mmGMCON_PGFSM_WRITE, 0x210000);  in kv_restore_regs_for_reset()
1318 	WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);  in kv_restore_regs_for_reset()
1321 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1323 	WREG32(mmGMCON_PGFSM_WRITE, 0x21003);  in kv_restore_regs_for_reset()
1324 	WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);  in kv_restore_regs_for_reset()
1327 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1329 	WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);  in kv_restore_regs_for_reset()
1330 	WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);  in kv_restore_regs_for_reset()
1333 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1335 	WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1336 	WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);  in kv_restore_regs_for_reset()
1339 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1341 	WREG32(mmGMCON_PGFSM_WRITE, 0x420000);  in kv_restore_regs_for_reset()
1342 	WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);  in kv_restore_regs_for_reset()
1345 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1347 	WREG32(mmGMCON_PGFSM_WRITE, 0x120202);  in kv_restore_regs_for_reset()
1348 	WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);  in kv_restore_regs_for_reset()
1351 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1353 	WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);  in kv_restore_regs_for_reset()
1354 	WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);  in kv_restore_regs_for_reset()
1357 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1359 	WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);  in kv_restore_regs_for_reset()
1360 	WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);  in kv_restore_regs_for_reset()
1363 		WREG32(mmGMCON_PGFSM_WRITE, 0);  in kv_restore_regs_for_reset()
1365 	WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);  in kv_restore_regs_for_reset()
1366 	WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);  in kv_restore_regs_for_reset()
1368 	WREG32(mmGMCON_MISC3, save->gmcon_misc3);  in kv_restore_regs_for_reset()
1369 	WREG32(mmGMCON_MISC, save->gmcon_misc);  in kv_restore_regs_for_reset()
1370 	WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);  in kv_restore_regs_for_reset()
1386 	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |  in cik_gpu_pci_config_reset()
1390 	WREG32(mmCP_MEC_CNTL,  in cik_gpu_pci_config_reset()
1396 	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
1400 	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
1445 	WREG32(mmBIOS_SCRATCH_3, tmp);  in cik_set_bios_scratch_engine_hung()