Lines Matching refs:tmp
119 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_start_smc() local
121 tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK; in amdgpu_ci_start_smc()
122 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_start_smc()
127 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_reset_smc() local
129 tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK; in amdgpu_ci_reset_smc()
130 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_reset_smc()
142 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_stop_smc_clock() local
144 tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK; in amdgpu_ci_stop_smc_clock()
146 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_ci_stop_smc_clock()
151 u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_start_smc_clock() local
153 tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK; in amdgpu_ci_start_smc_clock()
155 WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp); in amdgpu_ci_start_smc_clock()
171 u32 tmp; in amdgpu_ci_send_msg_to_smc() local
180 tmp = RREG32(mmSMC_RESP_0); in amdgpu_ci_send_msg_to_smc()
181 if (tmp != 0) in amdgpu_ci_send_msg_to_smc()
185 tmp = RREG32(mmSMC_RESP_0); in amdgpu_ci_send_msg_to_smc()
187 return (PPSMC_Result)tmp; in amdgpu_ci_send_msg_to_smc()
192 u32 tmp; in amdgpu_ci_wait_for_smc_inactive() local
199 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in amdgpu_ci_wait_for_smc_inactive()
200 if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0) in amdgpu_ci_wait_for_smc_inactive()