Lines Matching refs:table
1423 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits() local
1429 table->FpsHighT = cpu_to_be16(tmp); in ci_init_fps_limits()
1432 table->FpsLowT = cpu_to_be16(tmp); in ci_init_fps_limits()
2320 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
2325 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2326 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
2329 &table->VddcLevel[count]); in ci_populate_smc_vddc_table()
2332 table->VddcLevel[count].Smio |= in ci_populate_smc_vddc_table()
2335 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
2337 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); in ci_populate_smc_vddc_table()
2343 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddci_table() argument
2348 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2349 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
2352 &table->VddciLevel[count]); in ci_populate_smc_vddci_table()
2355 table->VddciLevel[count].Smio |= in ci_populate_smc_vddci_table()
2358 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
2360 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); in ci_populate_smc_vddci_table()
2366 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
2371 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2372 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
2375 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
2378 table->MvddLevel[count].Smio |= in ci_populate_smc_mvdd_table()
2381 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
2383 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
2389 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
2393 ret = ci_populate_smc_vddc_table(adev, table); in ci_populate_smc_voltage_tables()
2397 ret = ci_populate_smc_vddci_table(adev, table); in ci_populate_smc_voltage_tables()
2401 ret = ci_populate_smc_mvdd_table(adev, table); in ci_populate_smc_voltage_tables()
2727 SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
2734 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2736 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2738 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2739 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2740 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
2749 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
2755 table->UvdLevelCount = in ci_populate_smc_uvd_level()
2758 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2759 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2761 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2763 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2765 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2769 table->UvdLevel[count].VclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2773 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2777 table->UvdLevel[count].DclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2781 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2783 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2784 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
2785 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
2792 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
2798 table->VceLevelCount = in ci_populate_smc_vce_level()
2801 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2802 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2804 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2806 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2810 table->VceLevel[count].Frequency, false, ÷rs); in ci_populate_smc_vce_level()
2814 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2816 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2817 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
2825 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
2831 table->AcpLevelCount = (u8) in ci_populate_smc_acp_level()
2834 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2835 table->AcpLevel[count].Frequency = in ci_populate_smc_acp_level()
2837 table->AcpLevel[count].MinVoltage = in ci_populate_smc_acp_level()
2839 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
2843 table->AcpLevel[count].Frequency, false, ÷rs); in ci_populate_smc_acp_level()
2847 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2849 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
2850 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
2857 SMU7_Discrete_DpmTable *table) in ci_populate_smc_samu_level() argument
2863 table->SamuLevelCount = in ci_populate_smc_samu_level()
2866 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2867 table->SamuLevel[count].Frequency = in ci_populate_smc_samu_level()
2869 table->SamuLevel[count].MinVoltage = in ci_populate_smc_samu_level()
2871 table->SamuLevel[count].MinPhases = 1; in ci_populate_smc_samu_level()
2875 table->SamuLevel[count].Frequency, false, ÷rs); in ci_populate_smc_samu_level()
2879 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2881 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); in ci_populate_smc_samu_level()
2882 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); in ci_populate_smc_samu_level()
3096 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
3107 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
3110 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3112 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3114 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3116 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3120 table->ACPILevel.SclkFrequency, false, ÷rs); in ci_populate_smc_acpi_level()
3124 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
3125 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
3126 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
3134 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
3135 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
3136 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3137 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3138 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3139 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3140 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
3141 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
3143 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
3144 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
3145 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
3146 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
3147 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
3148 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
3149 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
3150 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
3151 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
3152 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
3153 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
3155 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
3156 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
3160 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3163 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3168 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
3170 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
3180 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); in ci_populate_smc_acpi_level()
3181 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); in ci_populate_smc_acpi_level()
3182 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
3184 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
3186 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
3188 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
3190 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
3192 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3193 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3195 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
3196 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
3197 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
3198 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
3199 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
3200 table->MemoryACPILevel.ActivityLevel = in ci_populate_smc_acpi_level()
3203 table->MemoryACPILevel.StutterEnable = false; in ci_populate_smc_acpi_level()
3204 table->MemoryACPILevel.StrobeEnable = false; in ci_populate_smc_acpi_level()
3205 table->MemoryACPILevel.EdcReadEnable = false; in ci_populate_smc_acpi_level()
3206 table->MemoryACPILevel.EdcWriteEnable = false; in ci_populate_smc_acpi_level()
3207 table->MemoryACPILevel.RttEnable = false; in ci_populate_smc_acpi_level()
3645 static int ci_find_boot_level(struct ci_single_dpm_table *table, in ci_find_boot_level() argument
3651 for(i = 0; i < table->count; i++) { in ci_find_boot_level()
3652 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3666 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table() local
3674 ci_populate_smc_voltage_tables(adev, table); in ci_init_smc_table()
3679 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
3682 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
3685 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
3702 ci_populate_smc_link_level(adev, table); in ci_init_smc_table()
3704 ret = ci_populate_smc_acpi_level(adev, table); in ci_init_smc_table()
3708 ret = ci_populate_smc_vce_level(adev, table); in ci_init_smc_table()
3712 ret = ci_populate_smc_acp_level(adev, table); in ci_init_smc_table()
3716 ret = ci_populate_smc_samu_level(adev, table); in ci_init_smc_table()
3724 ret = ci_populate_smc_uvd_level(adev, table); in ci_init_smc_table()
3728 table->UvdBootLevel = 0; in ci_init_smc_table()
3729 table->VceBootLevel = 0; in ci_init_smc_table()
3730 table->AcpBootLevel = 0; in ci_init_smc_table()
3731 table->SamuBootLevel = 0; in ci_init_smc_table()
3732 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3733 table->MemoryBootLevel = 0; in ci_init_smc_table()
3743 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3744 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3745 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3753 table->UVDInterval = 1; in ci_init_smc_table()
3754 table->VCEInterval = 1; in ci_init_smc_table()
3755 table->ACPInterval = 1; in ci_init_smc_table()
3756 table->SAMUInterval = 1; in ci_init_smc_table()
3757 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
3758 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
3759 table->GraphicsInterval = 1; in ci_init_smc_table()
3760 table->VoltageInterval = 1; in ci_init_smc_table()
3761 table->ThermalInterval = 1; in ci_init_smc_table()
3762 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3764 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3766 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
3767 table->MemoryInterval = 1; in ci_init_smc_table()
3768 table->VoltageResponseTime = 0; in ci_init_smc_table()
3769 table->VddcVddciDelta = 4000; in ci_init_smc_table()
3770 table->PhaseResponseTime = 0; in ci_init_smc_table()
3771 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
3772 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3773 table->PCIeGenInterval = 1; in ci_init_smc_table()
3775 table->SVI2Enable = 1; in ci_init_smc_table()
3777 table->SVI2Enable = 0; in ci_init_smc_table()
3779 table->ThermGpio = 17; in ci_init_smc_table()
3780 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3782 table->SystemFlags = cpu_to_be32(table->SystemFlags); in ci_init_smc_table()
3783 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); in ci_init_smc_table()
3784 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); in ci_init_smc_table()
3785 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); in ci_init_smc_table()
3786 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); in ci_init_smc_table()
3787 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); in ci_init_smc_table()
3788 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); in ci_init_smc_table()
3789 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); in ci_init_smc_table()
3790 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); in ci_init_smc_table()
3791 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); in ci_init_smc_table()
3792 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); in ci_init_smc_table()
3793 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
3794 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
3795 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
3800 (u8 *)&table->SystemFlags, in ci_init_smc_table()
4208 struct amdgpu_vce_clock_voltage_dependency_table *table = in ci_get_vce_boot_level() local
4211 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
4212 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4216 return table->count - 1; in ci_get_vce_boot_level()
4474 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
4479 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
4482 switch(table->mc_reg_address[i].s1) { in ci_set_mc_special_registers()
4485 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in ci_set_mc_special_registers()
4486 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in ci_set_mc_special_registers()
4487 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4488 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4489 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
4496 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in ci_set_mc_special_registers()
4497 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; in ci_set_mc_special_registers()
4498 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4499 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4500 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4502 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
4509 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()
4510 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()
4511 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4512 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4513 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
4522 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; in ci_set_mc_special_registers()
4523 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; in ci_set_mc_special_registers()
4524 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4525 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4526 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4538 table->last = j; in ci_set_mc_special_registers()
4616 static void ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
4620 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4621 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
4622 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
4623 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
4624 table->valid_flag |= 1 << i; in ci_set_valid_flag()
4631 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
4636 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4637 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
4638 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ci_set_s0_mc_reg_index()
4639 address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
4643 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, in ci_copy_vbios_mc_reg_table() argument
4648 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_copy_vbios_mc_reg_table()
4650 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ci_copy_vbios_mc_reg_table()
4653 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4654 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_mc_reg_table()
4656 ci_table->last = table->last; in ci_copy_vbios_mc_reg_table()
4658 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4660 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_mc_reg_table()
4661 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4663 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_mc_reg_table()
4665 ci_table->num_entries = table->num_entries; in ci_copy_vbios_mc_reg_table()
4671 struct ci_mc_reg_table *table) in ci_register_patching_mc_seq() argument
4683 for (i = 0; i < table->last; i++) { in ci_register_patching_mc_seq()
4684 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_register_patching_mc_seq()
4686 switch (table->mc_reg_address[i].s1) { in ci_register_patching_mc_seq()
4688 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4689 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4690 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4691 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4692 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | in ci_register_patching_mc_seq()
4697 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4698 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4699 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4700 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4701 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4706 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4707 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4708 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4709 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4710 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4715 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4716 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4717 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4718 table->mc_reg_table_entry[k].mc_data[i] = 0; in ci_register_patching_mc_seq()
4722 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4723 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4724 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4725 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4727 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4728 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4729 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4734 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4735 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4736 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4737 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4739 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4740 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4741 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4763 struct atom_mc_reg_table *table; in ci_initialize_mc_reg_table() local
4768 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
4769 if (!table) in ci_initialize_mc_reg_table()
4793 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); in ci_initialize_mc_reg_table()
4797 ret = ci_copy_vbios_mc_reg_table(table, ci_table); in ci_initialize_mc_reg_table()
4814 kfree(table); in ci_initialize_mc_reg_table()
5122 struct amdgpu_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
5126 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
5127 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
5128 ci_patch_with_vddc_leakage(adev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
5133 struct amdgpu_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
5137 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
5138 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
5139 ci_patch_with_vddci_leakage(adev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
5144 struct amdgpu_vce_clock_voltage_dependency_table *table) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
5148 if (table) { in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
5149 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
5150 ci_patch_with_vddc_leakage(adev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
5155 struct amdgpu_uvd_clock_voltage_dependency_table *table) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
5159 if (table) { in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5160 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5161 ci_patch_with_vddc_leakage(adev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5166 struct amdgpu_phase_shedding_limits_table *table) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
5170 if (table) { in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5171 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5172 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5177 struct amdgpu_clock_and_voltage_limits *table) in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
5179 if (table) { in ci_patch_clock_voltage_limits_with_vddc_leakage()
5180 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5181 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5186 struct amdgpu_cac_leakage_table *table) in ci_patch_cac_leakage_table_with_vddc_leakage() argument
5190 if (table) { in ci_patch_cac_leakage_table_with_vddc_leakage()
5191 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
5192 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()