Lines Matching refs:pi
313 struct ci_power_info *pi = adev->pm.dpm.priv; in ci_get_pi() local
315 return pi; in ci_get_pi()
327 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_powertune_defaults() local
337 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
343 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
347 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
351 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
361 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
365 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
367 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
368 pi->caps_cac = false; in ci_initialize_powertune_defaults()
369 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
370 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
371 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
372 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
374 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
375 pi->caps_cac = true; in ci_initialize_powertune_defaults()
377 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
379 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
380 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
381 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
392 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_vddc_vid_sidd() local
393 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
394 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
395 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
421 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_vddc_vid() local
422 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
425 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
428 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
429 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
436 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_svi_load_line() local
437 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
439 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
440 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
441 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
442 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
449 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_tdc_limit() local
450 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
454 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
455 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
457 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
464 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_dw8() local
465 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
472 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
473 pi->sram_end); in ci_populate_dw8()
477 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
484 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_fuzzy_fan() local
491 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
499 struct ci_power_info *pi = ci_get_pi(adev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
500 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
501 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
523 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
524 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
531 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_vddc_base_leakage_sidd() local
532 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
533 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
540 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
541 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
548 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_parameters_in_dpm_table() local
549 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
550 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
561 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
563 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
596 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_pm_base() local
600 if (pi->caps_power_containment) { in ci_populate_pm_base()
604 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
632 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
633 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
643 struct ci_power_info *pi = ci_get_pi(adev); in ci_do_enable_didt() local
646 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
655 if (pi->caps_db_ramping) { in ci_do_enable_didt()
664 if (pi->caps_td_ramping) { in ci_do_enable_didt()
673 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
733 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_didt() local
736 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
737 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
758 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_power_containment() local
763 pi->power_containment_features = 0; in ci_enable_power_containment()
764 if (pi->caps_power_containment) { in ci_enable_power_containment()
765 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
770 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
773 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
778 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
781 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
791 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
798 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
799 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
802 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
805 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
807 pi->power_containment_features = 0; in ci_enable_power_containment()
816 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_smc_cac() local
820 if (pi->caps_cac) { in ci_enable_smc_cac()
825 pi->cac_enabled = false; in ci_enable_smc_cac()
827 pi->cac_enabled = true; in ci_enable_smc_cac()
829 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
831 pi->cac_enabled = false; in ci_enable_smc_cac()
841 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_thermal_based_sclk_dpm() local
844 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
859 struct ci_power_info *pi = ci_get_pi(adev); in ci_power_control_set_level() local
867 if (pi->caps_power_containment) { in ci_power_control_set_level()
881 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_powergate_uvd() local
883 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
886 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
907 struct ci_power_info *pi = ci_get_pi(adev); in ci_apply_state_adjust_rules() local
928 pi->battery_state = true; in ci_apply_state_adjust_rules()
930 pi->battery_state = false; in ci_apply_state_adjust_rules()
1044 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_set_static_mode() local
1047 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
1050 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
1053 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
1054 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
1068 struct ci_power_info *pi = ci_get_pi(adev); in ci_thermal_setup_fan_table() local
1077 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1132 pi->fan_table_start, in ci_thermal_setup_fan_table()
1135 pi->sram_end); in ci_thermal_setup_fan_table()
1147 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_start_smc_fan_control() local
1150 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1169 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1177 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_stop_smc_fan_control() local
1181 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1221 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_fan_speed_percent() local
1226 if (pi->fan_is_controlled_by_smc) in ci_dpm_set_fan_speed_percent()
1267 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_fan_control_mode() local
1270 if (pi->fan_is_controlled_by_smc) in ci_dpm_get_fan_control_mode()
1332 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_set_default_mode() local
1335 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1337 tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; in ci_fan_ctrl_set_default_mode()
1341 tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; in ci_fan_ctrl_set_default_mode()
1343 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1402 struct ci_power_info *pi = ci_get_pi(adev);
1405 pi->soft_regs_start + reg_offset,
1406 value, pi->sram_end);
1413 struct ci_power_info *pi = ci_get_pi(adev); in ci_write_smc_soft_register() local
1416 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1417 value, pi->sram_end); in ci_write_smc_soft_register()
1422 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_fps_limits() local
1423 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1425 if (pi->caps_fps) { in ci_init_fps_limits()
1438 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_sclk_t() local
1442 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1443 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1446 pi->dpm_table_start + in ci_update_sclk_t()
1449 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1458 struct ci_power_info *pi = ci_get_pi(adev); in ci_get_leakage_voltages() local
1463 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1464 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1472 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1473 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1474 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1484 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1485 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1486 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1489 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1490 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1491 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1500 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_dpm_event_sources() local
1535 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1551 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_auto_throttle_source() local
1554 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1555 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1556 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1559 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1560 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1561 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1574 struct ci_power_info *pi = ci_get_pi(adev); in ci_unfreeze_sclk_mclk_dpm() local
1577 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1580 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1581 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1587 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1588 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1594 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1600 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_sclk_mclk_dpm() local
1604 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1610 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1629 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1635 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1647 struct ci_power_info *pi = ci_get_pi(adev); in ci_start_dpm() local
1672 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1683 struct ci_power_info *pi = ci_get_pi(adev); in ci_freeze_sclk_mclk_dpm() local
1686 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1689 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1690 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1696 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1697 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1708 struct ci_power_info *pi = ci_get_pi(adev); in ci_stop_dpm() local
1721 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1753 struct ci_power_info *pi = ci_get_pi(adev);
1765 if (pi->caps_automatic_dc_transition) {
1798 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_sclk() local
1800 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1812 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_mclk() local
1814 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1826 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_pcie() local
1828 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1840 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_power_limit() local
1842 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1916 struct ci_power_info *pi = ci_get_pi(adev); in ci_process_firmware_header() local
1923 &tmp, pi->sram_end); in ci_process_firmware_header()
1927 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1932 &tmp, pi->sram_end); in ci_process_firmware_header()
1936 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1941 &tmp, pi->sram_end); in ci_process_firmware_header()
1945 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1950 &tmp, pi->sram_end); in ci_process_firmware_header()
1954 pi->fan_table_start = tmp; in ci_process_firmware_header()
1959 &tmp, pi->sram_end); in ci_process_firmware_header()
1963 pi->arb_table_start = tmp; in ci_process_firmware_header()
1970 struct ci_power_info *pi = ci_get_pi(adev); in ci_read_clock_registers() local
1972 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1974 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1976 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1978 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1980 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1982 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1984 pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL); in ci_read_clock_registers()
1985 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1986 pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1987 pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1988 pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL); in ci_read_clock_registers()
1989 pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1990 pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1991 pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1); in ci_read_clock_registers()
1992 pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2); in ci_read_clock_registers()
1997 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_sclk_t() local
1999 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
2063 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_ds_master_switch() local
2066 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2074 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2119 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_spread_spectrum() local
2123 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2196 struct ci_power_info *pi = ci_get_pi(adev); in ci_upload_firmware() local
2208 ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end); in ci_upload_firmware()
2237 struct ci_power_info *pi = ci_get_pi(adev); in ci_construct_voltage_tables() local
2240 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2243 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2246 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2249 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2254 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2256 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2258 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2261 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2264 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2267 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2272 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2274 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2276 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2279 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2282 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2285 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2290 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2292 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2322 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_vddc_table() local
2325 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2328 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2331 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2333 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2346 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_vddci_table() local
2348 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2351 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2354 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2356 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2368 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_mvdd_table() local
2371 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2374 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2377 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2379 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2411 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_mvdd_value() local
2414 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2417 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2516 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_arb_table_index() local
2520 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start, in ci_init_arb_table_index()
2521 &tmp, pi->sram_end); in ci_init_arb_table_index()
2528 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start, in ci_init_arb_table_index()
2529 tmp, pi->sram_end); in ci_init_arb_table_index()
2648 struct ci_power_info *pi = ci_get_pi(adev); in ci_do_program_memory_timing_parameters() local
2655 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2656 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2658 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2659 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2668 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2671 pi->sram_end); in ci_do_program_memory_timing_parameters()
2678 struct ci_power_info *pi = ci_get_pi(adev); in ci_program_memory_timing_parameters() local
2680 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2690 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_initial_state() local
2696 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2704 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2729 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_link_level() local
2730 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2743 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2744 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2894 struct ci_power_info *pi = ci_get_pi(adev); in ci_calculate_mclk_params() local
2895 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2896 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2897 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2898 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2899 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2900 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2901 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2902 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2903 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2930 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2984 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_single_memory_level() local
3014 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
3025 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
3035 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
3036 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
3037 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
3042 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
3043 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
3049 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
3050 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
3053 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
3054 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
3064 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
3098 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_acpi_level() local
3101 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
3102 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
3103 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
3104 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
3109 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
3110 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3112 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3114 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3136 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3137 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3138 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3139 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3158 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3159 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3161 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3164 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3183 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3185 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3187 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3189 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3191 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3192 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3193 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3201 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3215 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_ulv() local
3216 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3233 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_ulv_level() local
3240 pi->ulv.supported = false; in ci_populate_ulv_level()
3244 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3258 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3271 struct ci_power_info *pi = ci_get_pi(adev); in ci_calculate_sclk_params() local
3273 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3274 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3275 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3276 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3295 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3328 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_single_graphic_level() local
3346 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3362 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3387 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_all_graphic_levels() local
3388 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3389 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3393 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3401 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3402 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3406 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3408 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3412 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3413 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3418 pi->sram_end); in ci_populate_all_graphic_levels()
3433 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_all_memory_levels() local
3434 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3435 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3439 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3449 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3456 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3457 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3458 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3459 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3462 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3464 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3465 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3468 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3473 pi->sram_end); in ci_populate_all_memory_levels()
3501 struct ci_power_info *pi = ci_get_pi(adev); in ci_setup_default_pcie_tables() local
3503 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3506 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3507 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3508 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3509 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3510 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3511 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3515 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3519 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3520 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3521 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3523 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3524 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3525 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3526 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3527 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3528 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3529 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3530 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3531 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3532 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3533 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3534 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3535 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3536 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3537 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3538 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3539 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3540 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3542 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3549 struct ci_power_info *pi = ci_get_pi(adev); in ci_setup_default_dpm_tables() local
3567 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3570 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3573 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3576 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3579 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3582 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3585 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3588 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3590 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3592 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3594 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3598 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3601 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3603 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3605 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3607 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3612 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3614 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3616 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3618 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3623 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3625 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3627 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3633 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3635 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3637 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3663 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_smc_table() local
3664 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3666 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3673 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3688 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3735 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3736 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3737 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3739 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3740 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3741 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3743 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3744 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3745 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3762 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3764 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3772 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3774 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3798 pi->dpm_table_start + in ci_init_smc_table()
3802 pi->sram_end); in ci_init_smc_table()
3828 struct ci_power_info *pi = ci_get_pi(adev); in ci_trim_pcie_dpm_states() local
3829 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3859 struct ci_power_info *pi = ci_get_pi(adev); in ci_trim_dpm_states() local
3871 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3876 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3923 struct ci_power_info *pi = ci_get_pi(adev); in ci_upload_dpm_level_enable_mask() local
3928 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3929 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3932 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3938 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3939 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3942 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3949 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3950 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3953 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3966 struct ci_power_info *pi = ci_get_pi(adev); in ci_find_dpm_states_clocks_in_dpm_table() local
3968 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3970 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3974 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3982 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3986 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3995 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3999 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
4005 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
4009 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4012 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
4015 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
4018 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
4021 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
4027 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
4038 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_uvd_dpm() local
4048 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
4052 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
4054 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
4061 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
4063 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
4064 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
4065 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
4068 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
4071 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
4072 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
4073 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
4076 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
4087 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_vce_dpm() local
4097 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
4100 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
4102 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
4109 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
4120 struct ci_power_info *pi = ci_get_pi(adev);
4130 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4133 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4135 if (!pi->caps_samu_dpm)
4142 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4151 struct ci_power_info *pi = ci_get_pi(adev);
4161 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4164 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4166 if (!pi->caps_acp_dpm)
4173 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4184 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_uvd_dpm() local
4188 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4190 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4192 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4197 tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT); in ci_update_uvd_dpm()
4223 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_vce_dpm() local
4235 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev); in ci_update_vce_dpm()
4238 tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT); in ci_update_vce_dpm()
4263 struct ci_power_info *pi = ci_get_pi(adev);
4267 pi->smc_state_table.AcpBootLevel = 0;
4271 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4282 struct ci_power_info *pi = ci_get_pi(adev); in ci_generate_dpm_level_enable_mask() local
4289 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4290 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4291 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4292 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4293 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4294 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4295 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4296 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4297 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4299 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4300 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4320 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_performance_level() local
4325 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4326 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4328 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4345 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4346 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4348 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4365 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4366 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4368 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4385 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4386 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4388 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4406 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4407 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4409 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4422 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4423 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4425 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4438 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4439 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4441 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4455 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4762 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_mc_reg_table() local
4764 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4822 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_mc_reg_addresses() local
4825 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4826 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4829 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4830 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4858 struct ci_power_info *pi = ci_get_pi(adev); in ci_convert_mc_reg_table_entry_to_smc() local
4861 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4862 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4866 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4869 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4870 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4871 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4877 struct ci_power_info *pi = ci_get_pi(adev); in ci_convert_mc_reg_table_to_smc() local
4880 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4882 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4888 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_initial_mc_reg_table() local
4891 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4893 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4896 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4899 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4900 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4902 pi->sram_end); in ci_populate_initial_mc_reg_table()
4907 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_and_upload_mc_reg_table() local
4909 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4912 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4914 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4917 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4919 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4921 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4922 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4988 struct ci_power_info *pi = ci_get_pi(adev); in ci_request_link_speed_change_before_state_change() local
4993 if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4996 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4998 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4999 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
5006 pi->force_pcie_gen = AMDGPU_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
5014 pi->force_pcie_gen = ci_get_current_pcie_speed(adev); in ci_request_link_speed_change_before_state_change()
5019 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
5027 struct ci_power_info *pi = ci_get_pi(adev); in ci_notify_link_speed_change_after_state_change() local
5032 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
5052 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_private_data_variables_based_on_pptable() local
5073 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
5074 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
5077 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
5078 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
5095 struct ci_power_info *pi = ci_get_pi(adev); in ci_patch_with_vddc_leakage() local
5096 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
5109 struct ci_power_info *pi = ci_get_pi(adev); in ci_patch_with_vddci_leakage() local
5110 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5230 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_current_ps() local
5232 pi->current_rps = *rps; in ci_update_current_ps()
5233 pi->current_ps = *new_ps; in ci_update_current_ps()
5234 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5241 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_requested_ps() local
5243 pi->requested_rps = *rps; in ci_update_requested_ps()
5244 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5245 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5250 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_pre_set_power_state() local
5256 ci_apply_state_adjust_rules(adev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5263 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_post_set_power_state() local
5264 struct amdgpu_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5279 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_enable() local
5285 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5293 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5296 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5298 if (pi->dynamic_ss) in ci_dpm_enable()
5300 if (pi->thermal_protection) in ci_dpm_enable()
5330 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5428 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_disable() local
5443 if (pi->thermal_protection) in ci_dpm_disable()
5464 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_power_state() local
5465 struct amdgpu_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5466 struct amdgpu_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5470 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5499 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5521 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5589 struct ci_power_info *pi = ci_get_pi(adev); in ci_parse_pplib_clock_info() local
5601 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5602 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5605 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5609 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5613 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5614 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5615 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5620 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5621 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5622 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5623 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5628 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5629 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5630 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5631 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5632 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5633 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5634 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5635 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5636 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5639 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5640 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5641 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5642 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5643 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5644 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5645 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5646 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5647 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5838 struct ci_power_info *pi; in ci_dpm_init() local
5842 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5843 if (pi == NULL) in ci_dpm_init()
5845 adev->pm.dpm.priv = pi; in ci_dpm_init()
5849 pi->sys_pcie_mask = 0; in ci_dpm_init()
5851 pi->sys_pcie_mask = mask; in ci_dpm_init()
5852 pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; in ci_dpm_init()
5854 pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1; in ci_dpm_init()
5855 pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3; in ci_dpm_init()
5856 pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1; in ci_dpm_init()
5857 pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3; in ci_dpm_init()
5859 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5860 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5861 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5862 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5864 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state); in ci_dpm_init()
5888 pi->dll_default_on = false; in ci_dpm_init()
5889 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5891 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5892 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5893 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5894 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5895 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5896 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5897 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5898 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5900 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5902 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5903 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5904 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5905 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5907 pi->caps_sclk_ds = true; in ci_dpm_init()
5909 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5910 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5911 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5912 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5916 pi->caps_fps = false; in ci_dpm_init()
5918 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5920 pi->caps_uvd_dpm = true; in ci_dpm_init()
5921 pi->caps_vce_dpm = true; in ci_dpm_init()
5953 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5954 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5955 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5957 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5958 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5959 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5962 pi->uvd_enabled = false; in ci_dpm_init()
5964 dpm_table = &pi->smc_state_table; in ci_dpm_init()
6013 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
6014 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
6015 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
6017 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
6019 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
6023 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
6025 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
6032 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
6034 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
6039 pi->vddc_phase_shed_control = true; in ci_dpm_init()
6042 pi->pcie_performance_request = in ci_dpm_init()
6045 pi->pcie_performance_request = false; in ci_dpm_init()
6050 pi->caps_sclk_ss_support = true; in ci_dpm_init()
6051 pi->caps_mclk_ss_support = true; in ci_dpm_init()
6052 pi->dynamic_ss = true; in ci_dpm_init()
6054 pi->caps_sclk_ss_support = false; in ci_dpm_init()
6055 pi->caps_mclk_ss_support = false; in ci_dpm_init()
6056 pi->dynamic_ss = true; in ci_dpm_init()
6060 pi->thermal_protection = true; in ci_dpm_init()
6062 pi->thermal_protection = false; in ci_dpm_init()
6064 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
6066 pi->uvd_power_gated = false; in ci_dpm_init()
6074 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
6083 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_debugfs_print_current_performance_level() local
6084 struct amdgpu_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
6088 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
6114 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_sclk() local
6115 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
6125 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_mclk() local
6126 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()