939 			if (ps->performance_levels[i].mclk > max_limits->mclk)  in ci_apply_state_adjust_rules()
940 				ps->performance_levels[i].mclk = max_limits->mclk;  in ci_apply_state_adjust_rules()
941 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ci_apply_state_adjust_rules()
942 				ps->performance_levels[i].sclk = max_limits->sclk;  in ci_apply_state_adjust_rules()
949 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
950 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
952 		mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
953 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
963 	ps->performance_levels[0].sclk = sclk;  in ci_apply_state_adjust_rules()
964 	ps->performance_levels[0].mclk = mclk;  in ci_apply_state_adjust_rules()
966 	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)  in ci_apply_state_adjust_rules()
967 		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
970 		if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)  in ci_apply_state_adjust_rules()
971 			ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;  in ci_apply_state_adjust_rules()
973 		if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)  in ci_apply_state_adjust_rules()
974 			ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
2695 		    boot_state->performance_levels[0].sclk) {  in ci_populate_smc_initial_state()
2703 		    boot_state->performance_levels[0].mclk) {  in ci_populate_smc_initial_state()
3872 				  state->performance_levels[0].sclk,  in ci_trim_dpm_states()
3873 				  state->performance_levels[high_limit_count].sclk);  in ci_trim_dpm_states()
3877 				  state->performance_levels[0].mclk,  in ci_trim_dpm_states()
3878 				  state->performance_levels[high_limit_count].mclk);  in ci_trim_dpm_states()
3881 				state->performance_levels[0].pcie_gen,  in ci_trim_dpm_states()
3882 				state->performance_levels[0].pcie_lane,  in ci_trim_dpm_states()
3883 				state->performance_levels[high_limit_count].pcie_gen,  in ci_trim_dpm_states()
3884 				state->performance_levels[high_limit_count].pcie_lane);  in ci_trim_dpm_states()
3969 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3971 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()
4007 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4008 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4941 		pcie_speed = state->performance_levels[i].pcie_gen;  in ci_get_maximum_link_speed()
5591 	struct ci_pl *pl = &ps->performance_levels[index];  in ci_parse_pplib_clock_info()
6105 		pl = &ps->performance_levels[i];  in ci_dpm_print_power_state()
6118 		return requested_state->performance_levels[0].sclk;  in ci_dpm_get_sclk()
6120 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()
6129 		return requested_state->performance_levels[0].mclk;  in ci_dpm_get_mclk()
6131 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()