Lines Matching refs:memory_level
2982 SMU7_Discrete_MemoryLevel *memory_level) in ci_populate_single_memory_level() argument
2991 memory_clock, &memory_level->MinVddc); in ci_populate_single_memory_level()
2999 memory_clock, &memory_level->MinVddci); in ci_populate_single_memory_level()
3007 memory_clock, &memory_level->MinMvdd); in ci_populate_single_memory_level()
3012 memory_level->MinVddcPhases = 1; in ci_populate_single_memory_level()
3018 &memory_level->MinVddcPhases); in ci_populate_single_memory_level()
3020 memory_level->EnabledForThrottle = 1; in ci_populate_single_memory_level()
3021 memory_level->EnabledForActivity = 1; in ci_populate_single_memory_level()
3022 memory_level->UpH = 0; in ci_populate_single_memory_level()
3023 memory_level->DownH = 100; in ci_populate_single_memory_level()
3024 memory_level->VoltageDownH = 0; in ci_populate_single_memory_level()
3025 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
3027 memory_level->StutterEnable = false; in ci_populate_single_memory_level()
3028 memory_level->StrobeEnable = false; in ci_populate_single_memory_level()
3029 memory_level->EdcReadEnable = false; in ci_populate_single_memory_level()
3030 memory_level->EdcWriteEnable = false; in ci_populate_single_memory_level()
3031 memory_level->RttEnable = false; in ci_populate_single_memory_level()
3033 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_single_memory_level()
3040 memory_level->StutterEnable = true; in ci_populate_single_memory_level()
3044 memory_level->StrobeEnable = 1; in ci_populate_single_memory_level()
3047 memory_level->StrobeRatio = in ci_populate_single_memory_level()
3048 ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); in ci_populate_single_memory_level()
3051 memory_level->EdcReadEnable = true; in ci_populate_single_memory_level()
3055 memory_level->EdcWriteEnable = true; in ci_populate_single_memory_level()
3057 if (memory_level->StrobeEnable) { in ci_populate_single_memory_level()
3067 memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock); in ci_populate_single_memory_level()
3071 …ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s… in ci_populate_single_memory_level()
3075 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE); in ci_populate_single_memory_level()
3076 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases); in ci_populate_single_memory_level()
3077 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE); in ci_populate_single_memory_level()
3078 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE); in ci_populate_single_memory_level()
3080 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency); in ci_populate_single_memory_level()
3081 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel); in ci_populate_single_memory_level()
3082 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl); in ci_populate_single_memory_level()
3083 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1); in ci_populate_single_memory_level()
3084 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2); in ci_populate_single_memory_level()
3085 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl); in ci_populate_single_memory_level()
3086 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl); in ci_populate_single_memory_level()
3087 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl); in ci_populate_single_memory_level()
3088 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl); in ci_populate_single_memory_level()
3089 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1); in ci_populate_single_memory_level()
3090 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2); in ci_populate_single_memory_level()