244 static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)  in ci_get_ddr3_mclk_frequency_ratio()  argument
248 	if (memory_clock < 10000)  in ci_get_ddr3_mclk_frequency_ratio()
250 	else if (memory_clock >= 80000)  in ci_get_ddr3_mclk_frequency_ratio()
253 		mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);  in ci_get_ddr3_mclk_frequency_ratio()
257 static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)  in ci_get_mclk_frequency_ratio()  argument
262 		if (memory_clock < 12500)  in ci_get_mclk_frequency_ratio()
264 		else if (memory_clock > 47500)  in ci_get_mclk_frequency_ratio()
267 			mc_para_index = (u8)((memory_clock - 10000) / 2500);  in ci_get_mclk_frequency_ratio()
269 		if (memory_clock < 65000)  in ci_get_mclk_frequency_ratio()
271 		else if (memory_clock > 135000)  in ci_get_mclk_frequency_ratio()
274 			mc_para_index = (u8)((memory_clock - 60000) / 5000);  in ci_get_mclk_frequency_ratio()
2598 					const u32 memory_clock,  in ci_register_patching_mc_arb()  argument
2610 		if ((memory_clock > 100000) && (memory_clock <= 125000)) {  in ci_register_patching_mc_arb()
2614 		} else if ((memory_clock > 125000) && (memory_clock <= 137500)) {  in ci_register_patching_mc_arb()
2889 				    u32 memory_clock,  in ci_calculate_mclk_params()  argument
2907 	ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);  in ci_calculate_mclk_params()
2937 			freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);  in ci_calculate_mclk_params()
2939 			freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);  in ci_calculate_mclk_params()
2966 	mclk->MclkFrequency = memory_clock;  in ci_calculate_mclk_params()
2981 					   u32 memory_clock,  in ci_populate_single_memory_level()  argument
2991 						    memory_clock, &memory_level->MinVddc);  in ci_populate_single_memory_level()
2999 						    memory_clock, &memory_level->MinVddci);  in ci_populate_single_memory_level()
3007 						    memory_clock, &memory_level->MinMvdd);  in ci_populate_single_memory_level()
3017 						      memory_clock,  in ci_populate_single_memory_level()
3036 	    (memory_clock <= pi->mclk_stutter_mode_threshold) &&  in ci_populate_single_memory_level()
3043 	    (memory_clock <= pi->mclk_strobe_mode_threshold))  in ci_populate_single_memory_level()
3048 			ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);  in ci_populate_single_memory_level()
3050 		    (memory_clock > pi->mclk_edc_enable_threshold))  in ci_populate_single_memory_level()
3054 		    (memory_clock > pi->mclk_edc_wr_enable_threshold))  in ci_populate_single_memory_level()
3058 			if (ci_get_mclk_frequency_ratio(memory_clock, true) >=  in ci_populate_single_memory_level()
3067 		memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);  in ci_populate_single_memory_level()
3071 …ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s…  in ci_populate_single_memory_level()
4855 						 const u32 memory_clock,  in ci_convert_mc_reg_table_entry_to_smc()  argument
4862 		if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)  in ci_convert_mc_reg_table_entry_to_smc()