550 	SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;  in ci_populate_bapm_parameters_in_dpm_table()  local
558 	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
559 	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
561 	dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;  in ci_populate_bapm_parameters_in_dpm_table()
562 	dpm_table->GpuTjMax =  in ci_populate_bapm_parameters_in_dpm_table()
564 	dpm_table->GpuTjHyst = 8;  in ci_populate_bapm_parameters_in_dpm_table()
566 	dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;  in ci_populate_bapm_parameters_in_dpm_table()
569 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);  in ci_populate_bapm_parameters_in_dpm_table()
570 		dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);  in ci_populate_bapm_parameters_in_dpm_table()
572 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
573 		dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
576 	dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);  in ci_populate_bapm_parameters_in_dpm_table()
583 				dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);  in ci_populate_bapm_parameters_in_dpm_table()
584 				dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);  in ci_populate_bapm_parameters_in_dpm_table()
2655 	for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {  in ci_do_program_memory_timing_parameters()
2656 		for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {  in ci_do_program_memory_timing_parameters()
2658 								   pi->dpm_table.sclk_table.dpm_levels[i].value,  in ci_do_program_memory_timing_parameters()
2659 								   pi->dpm_table.mclk_table.dpm_levels[j].value,  in ci_do_program_memory_timing_parameters()
2710 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)  in ci_get_dpm_level_enable_mask_value()  argument
2715 	for (i = dpm_table->count; i > 0; i--) {  in ci_get_dpm_level_enable_mask_value()
2717 		if (dpm_table->dpm_levels[i-1].enabled)  in ci_get_dpm_level_enable_mask_value()
2730 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_smc_link_level()  local
2733 	for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {  in ci_populate_smc_link_level()
2735 			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;  in ci_populate_smc_link_level()
2737 			amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);  in ci_populate_smc_link_level()
2743 	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;  in ci_populate_smc_link_level()
2745 		ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);  in ci_populate_smc_link_level()
3388 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_graphic_levels()  local
3398 	for (i = 0; i < dpm_table->sclk_table.count; i++) {  in ci_populate_all_graphic_levels()
3400 						       dpm_table->sclk_table.dpm_levels[i].value,  in ci_populate_all_graphic_levels()
3407 		if (i == (dpm_table->sclk_table.count - 1))  in ci_populate_all_graphic_levels()
3412 	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;  in ci_populate_all_graphic_levels()
3414 		ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);  in ci_populate_all_graphic_levels()
3434 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_memory_levels()  local
3444 	for (i = 0; i < dpm_table->mclk_table.count; i++) {  in ci_populate_all_memory_levels()
3445 		if (dpm_table->mclk_table.dpm_levels[i].value == 0)  in ci_populate_all_memory_levels()
3448 						      dpm_table->mclk_table.dpm_levels[i].value,  in ci_populate_all_memory_levels()
3454 	if ((dpm_table->mclk_table.count >= 2) &&  in ci_populate_all_memory_levels()
3464 	pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;  in ci_populate_all_memory_levels()
3466 		ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);  in ci_populate_all_memory_levels()
3468 	pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =  in ci_populate_all_memory_levels()
3481 				      struct ci_single_dpm_table* dpm_table,  in ci_reset_single_dpm_table()  argument
3486 	dpm_table->count = count;  in ci_reset_single_dpm_table()
3488 		dpm_table->dpm_levels[i].enabled = false;  in ci_reset_single_dpm_table()
3491 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,  in ci_setup_pcie_table_entry()  argument
3494 	dpm_table->dpm_levels[index].value = pcie_gen;  in ci_setup_pcie_table_entry()
3495 	dpm_table->dpm_levels[index].param1 = pcie_lanes;  in ci_setup_pcie_table_entry()
3496 	dpm_table->dpm_levels[index].enabled = true;  in ci_setup_pcie_table_entry()
3515 				  &pi->dpm_table.pcie_speed_table,  in ci_setup_default_pcie_tables()
3519 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3523 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3526 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,  in ci_setup_default_pcie_tables()
3529 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,  in ci_setup_default_pcie_tables()
3532 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,  in ci_setup_default_pcie_tables()
3535 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,  in ci_setup_default_pcie_tables()
3538 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,  in ci_setup_default_pcie_tables()
3542 	pi->dpm_table.pcie_speed_table.count = 6;  in ci_setup_default_pcie_tables()
3567 	memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));  in ci_setup_default_dpm_tables()
3570 				  &pi->dpm_table.sclk_table,  in ci_setup_default_dpm_tables()
3573 				  &pi->dpm_table.mclk_table,  in ci_setup_default_dpm_tables()
3576 				  &pi->dpm_table.vddc_table,  in ci_setup_default_dpm_tables()
3579 				  &pi->dpm_table.vddci_table,  in ci_setup_default_dpm_tables()
3582 				  &pi->dpm_table.mvdd_table,  in ci_setup_default_dpm_tables()
3585 	pi->dpm_table.sclk_table.count = 0;  in ci_setup_default_dpm_tables()
3588 		    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3590 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =  in ci_setup_default_dpm_tables()
3592 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3594 			pi->dpm_table.sclk_table.count++;  in ci_setup_default_dpm_tables()
3598 	pi->dpm_table.mclk_table.count = 0;  in ci_setup_default_dpm_tables()
3601 		    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3603 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =  in ci_setup_default_dpm_tables()
3605 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3607 			pi->dpm_table.mclk_table.count++;  in ci_setup_default_dpm_tables()
3612 		pi->dpm_table.vddc_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3614 		pi->dpm_table.vddc_table.dpm_levels[i].param1 =  in ci_setup_default_dpm_tables()
3616 		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3618 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;  in ci_setup_default_dpm_tables()
3623 			pi->dpm_table.vddci_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3625 			pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3627 		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3633 			pi->dpm_table.mvdd_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3635 			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3637 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3735 	ret = ci_find_boot_level(&pi->dpm_table.sclk_table,  in ci_init_smc_table()
3739 	ret = ci_find_boot_level(&pi->dpm_table.mclk_table,  in ci_init_smc_table()
3772 	table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;  in ci_init_smc_table()
3810 				      struct ci_single_dpm_table *dpm_table,  in ci_trim_single_dpm_states()  argument
3815 	for (i = 0; i < dpm_table->count; i++) {  in ci_trim_single_dpm_states()
3816 		if ((dpm_table->dpm_levels[i].value < low_limit) ||  in ci_trim_single_dpm_states()
3817 		    (dpm_table->dpm_levels[i].value > high_limit))  in ci_trim_single_dpm_states()
3818 			dpm_table->dpm_levels[i].enabled = false;  in ci_trim_single_dpm_states()
3820 			dpm_table->dpm_levels[i].enabled = true;  in ci_trim_single_dpm_states()
3829 	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;  in ci_trim_pcie_dpm_states()
3871 				  &pi->dpm_table.sclk_table,  in ci_trim_dpm_states()
3876 				  &pi->dpm_table.mclk_table,  in ci_trim_dpm_states()
3968 	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
3970 	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
4009 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
4016 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4019 		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4290 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);  in ci_generate_dpm_level_enable_mask()
4292 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);  in ci_generate_dpm_level_enable_mask()
4300 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);  in ci_generate_dpm_level_enable_mask()
4880 	for (i = 0; i < pi->dpm_table.mclk_table.count; i++)  in ci_convert_mc_reg_table_to_smc()
4882 						     pi->dpm_table.mclk_table.dpm_levels[i].value,  in ci_convert_mc_reg_table_to_smc()
4921 				    pi->dpm_table.mclk_table.count,  in ci_update_and_upload_mc_reg_table()
5834 	SMU7_Discrete_DpmTable *dpm_table;  in ci_dpm_init()  local
5964 	dpm_table = &pi->smc_state_table;  in ci_dpm_init()
5968 		dpm_table->VRHotGpio = gpio.shift;  in ci_dpm_init()
5971 		dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()
5977 		dpm_table->AcDcGpio = gpio.shift;  in ci_dpm_init()
5980 		dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()