313 	struct ci_power_info *pi = adev->pm.dpm.priv;  in ci_get_pi()
398 	if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)  in ci_populate_bapm_vddc_vid_sidd()
400 	if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)  in ci_populate_bapm_vddc_vid_sidd()
402 	if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=  in ci_populate_bapm_vddc_vid_sidd()
403 	    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)  in ci_populate_bapm_vddc_vid_sidd()
406 	for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {  in ci_populate_bapm_vddc_vid_sidd()
407 		if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {  in ci_populate_bapm_vddc_vid_sidd()
408 			lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);  in ci_populate_bapm_vddc_vid_sidd()
409 			hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);  in ci_populate_bapm_vddc_vid_sidd()
410 			hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);  in ci_populate_bapm_vddc_vid_sidd()
412 			lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);  in ci_populate_bapm_vddc_vid_sidd()
413 			hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);  in ci_populate_bapm_vddc_vid_sidd()
453 	tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;  in ci_populate_tdc_limit()
486 	if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||  in ci_populate_fuzzy_fan()
487 	    (adev->pm.dpm.fan.fan_output_sensitivity == 0))  in ci_populate_fuzzy_fan()
488 		adev->pm.dpm.fan.fan_output_sensitivity =  in ci_populate_fuzzy_fan()
489 			adev->pm.dpm.fan.default_fan_output_sensitivity;  in ci_populate_fuzzy_fan()
492 		cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);  in ci_populate_fuzzy_fan()
535 		adev->pm.dpm.dyn_state.cac_tdp_table;  in ci_populate_bapm_vddc_base_leakage_sidd()
552 		adev->pm.dpm.dyn_state.cac_tdp_table;  in ci_populate_bapm_parameters_in_dpm_table()
553 	struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;  in ci_populate_bapm_parameters_in_dpm_table()
787 						adev->pm.dpm.dyn_state.cac_tdp_table;  in ci_enable_power_containment()
861 		adev->pm.dpm.dyn_state.cac_tdp_table;  in ci_power_control_set_level()
869 			adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);  in ci_power_control_set_level()
914 		rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;  in ci_apply_state_adjust_rules()
915 		rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;  in ci_apply_state_adjust_rules()
921 	if ((adev->pm.dpm.new_active_crtc_count > 1) ||  in ci_apply_state_adjust_rules()
932 	if (adev->pm.dpm.ac_power)  in ci_apply_state_adjust_rules()
933 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ci_apply_state_adjust_rules()
935 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in ci_apply_state_adjust_rules()
937 	if (adev->pm.dpm.ac_power == false) {  in ci_apply_state_adjust_rules()
957 		if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)  in ci_apply_state_adjust_rules()
958 			sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;  in ci_apply_state_adjust_rules()
959 		if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)  in ci_apply_state_adjust_rules()
960 			mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;  in ci_apply_state_adjust_rules()
1008 	adev->pm.dpm.thermal.min_temp = low_temp;  in ci_thermal_set_temperature_range()
1009 	adev->pm.dpm.thermal.max_temp = high_temp;  in ci_thermal_set_temperature_range()
1078 		adev->pm.dpm.fan.ucode_fan_control = false;  in ci_thermal_setup_fan_table()
1086 		adev->pm.dpm.fan.ucode_fan_control = false;  in ci_thermal_setup_fan_table()
1090 	tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;  in ci_thermal_setup_fan_table()
1094 	t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;  in ci_thermal_setup_fan_table()
1095 	t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;  in ci_thermal_setup_fan_table()
1097 	pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;  in ci_thermal_setup_fan_table()
1098 	pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;  in ci_thermal_setup_fan_table()
1103 	fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);  in ci_thermal_setup_fan_table()
1104 	fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);  in ci_thermal_setup_fan_table()
1105 	fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);  in ci_thermal_setup_fan_table()
1112 	fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);  in ci_thermal_setup_fan_table()
1122 	fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *  in ci_thermal_setup_fan_table()
1139 		adev->pm.dpm.fan.ucode_fan_control = false;  in ci_thermal_setup_fan_table()
1158 							       adev->pm.dpm.fan.default_max_fan_pwm);  in ci_fan_ctrl_start_smc_fan_control()
1253 		if (adev->pm.dpm.fan.ucode_fan_control)  in ci_dpm_set_fan_control_mode()
1258 		if (adev->pm.dpm.fan.ucode_fan_control)  in ci_dpm_set_fan_control_mode()
1316 	if (adev->pm.dpm.fan.ucode_fan_control)
1349 	if (adev->pm.dpm.fan.ucode_fan_control) {  in ci_thermal_start_smc_fan_control()
1382 	if (adev->pm.dpm.fan.ucode_fan_control) {  in ci_thermal_start_thermal_controller()
1466 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {  in ci_get_leakage_voltages()
1568 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)  in ci_enable_vr_hot_gpio_interrupt()
1755 		adev->pm.dpm.dyn_state.cac_tdp_table;
2093 	if (adev->pm.dpm.new_active_crtc_count > 0)  in ci_program_display_gap()
2113 	ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));  in ci_program_display_gap()
2248 						&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in ci_construct_voltage_tables()
2266 						&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in ci_construct_voltage_tables()
2284 						&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,  in ci_construct_voltage_tables()
2415 		for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {  in ci_populate_mvdd_value()
2416 			if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {  in ci_populate_mvdd_value()
2422 		if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)  in ci_populate_mvdd_value()
2438 	if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)  in ci_get_std_voltage_value_sidd()
2441 	if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {  in ci_get_std_voltage_value_sidd()
2442 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in ci_get_std_voltage_value_sidd()
2444 			    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in ci_get_std_voltage_value_sidd()
2446 				if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)  in ci_get_std_voltage_value_sidd()
2449 					idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;  in ci_get_std_voltage_value_sidd()
2451 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;  in ci_get_std_voltage_value_sidd()
2453 					adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;  in ci_get_std_voltage_value_sidd()
2459 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {  in ci_get_std_voltage_value_sidd()
2461 				    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {  in ci_get_std_voltage_value_sidd()
2463 					if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)  in ci_get_std_voltage_value_sidd()
2466 						idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;  in ci_get_std_voltage_value_sidd()
2468 						adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;  in ci_get_std_voltage_value_sidd()
2470 						adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;  in ci_get_std_voltage_value_sidd()
2693 	for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {  in ci_populate_smc_initial_state()
2694 		if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=  in ci_populate_smc_initial_state()
2701 	for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {  in ci_populate_smc_initial_state()
2702 		if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=  in ci_populate_smc_initial_state()
2756 		adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;  in ci_populate_smc_uvd_level()
2760 			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;  in ci_populate_smc_uvd_level()
2762 			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;  in ci_populate_smc_uvd_level()
2764 			adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;  in ci_populate_smc_uvd_level()
2799 		adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;  in ci_populate_smc_vce_level()
2803 			adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;  in ci_populate_smc_vce_level()
2805 			(u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;  in ci_populate_smc_vce_level()
2832 		(adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);  in ci_populate_smc_acp_level()
2836 			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;  in ci_populate_smc_acp_level()
2838 			adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;  in ci_populate_smc_acp_level()
2864 		adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;  in ci_populate_smc_samu_level()
2868 			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;  in ci_populate_smc_samu_level()
2870 			adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;  in ci_populate_smc_samu_level()
2988 	if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {  in ci_populate_single_memory_level()
2990 						    &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,  in ci_populate_single_memory_level()
2996 	if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {  in ci_populate_single_memory_level()
2998 						    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,  in ci_populate_single_memory_level()
3004 	if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {  in ci_populate_single_memory_level()
3006 						    &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,  in ci_populate_single_memory_level()
3016 						      &adev->pm.dpm.dyn_state.phase_shedding_limits_table,  in ci_populate_single_memory_level()
3039 	    (adev->pm.dpm.new_active_crtc_count <= 2))  in ci_populate_single_memory_level()
3234 	u16 ulv_voltage = adev->pm.dpm.backbias_response_time;  in ci_populate_ulv_level()
3245 		if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)  in ci_populate_ulv_level()
3249 				adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;  in ci_populate_ulv_level()
3251 		if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)  in ci_populate_ulv_level()
3255 				((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *  in ci_populate_ulv_level()
3336 					    &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,  in ci_populate_single_graphic_level()
3348 						      &adev->pm.dpm.dyn_state.phase_shedding_limits_table,  in ci_populate_single_graphic_level()
3551 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in ci_setup_default_dpm_tables()
3553 		&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;  in ci_setup_default_dpm_tables()
3555 		&adev->pm.dpm.dyn_state.cac_leakage_table;  in ci_setup_default_dpm_tables()
3620 	allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;  in ci_setup_default_dpm_tables()
3630 	allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;  in ci_setup_default_dpm_tables()
3665 	struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;  in ci_init_smc_table()
3678 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)  in ci_init_smc_table()
3681 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)  in ci_init_smc_table()
3892 		&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;  in ci_apply_disp_minimum_voltage_request()
3894 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in ci_apply_disp_minimum_voltage_request()
3997 	if (adev->pm.dpm.current_active_crtc_count !=  in ci_find_dpm_states_clocks_in_dpm_table()
3998 	    adev->pm.dpm.new_active_crtc_count)  in ci_find_dpm_states_clocks_in_dpm_table()
4042 	if (adev->pm.dpm.ac_power)  in ci_enable_uvd_dpm()
4043 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ci_enable_uvd_dpm()
4045 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in ci_enable_uvd_dpm()
4050 		for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {  in ci_enable_uvd_dpm()
4051 			if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {  in ci_enable_uvd_dpm()
4091 	if (adev->pm.dpm.ac_power)  in ci_enable_vce_dpm()
4092 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ci_enable_vce_dpm()
4094 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;  in ci_enable_vce_dpm()
4098 		for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {  in ci_enable_vce_dpm()
4099 			if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {  in ci_enable_vce_dpm()
4124 	if (adev->pm.dpm.ac_power)
4125 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4127 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4131 		for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4132 …	if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4155 	if (adev->pm.dpm.ac_power)
4156 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4158 		max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4162 		for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4163 			if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4189 		    (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))  in ci_update_uvd_dpm()
4193 				adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;  in ci_update_uvd_dpm()
4209 		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;  in ci_get_vce_boot_level()
4468 	adev->pm.dpm.forced_level = level;  in ci_dpm_force_performance_level()
5054 		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;  in ci_set_private_data_variables_based_on_pptable()
5056 		&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;  in ci_set_private_data_variables_based_on_pptable()
5058 		&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;  in ci_set_private_data_variables_based_on_pptable()
5081 	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =  in ci_set_private_data_variables_based_on_pptable()
5083 	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =  in ci_set_private_data_variables_based_on_pptable()
5085 	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =  in ci_set_private_data_variables_based_on_pptable()
5087 	adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =  in ci_set_private_data_variables_based_on_pptable()
5200 								  &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);  in ci_patch_dependency_tables_with_leakage()
5202 								  &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);  in ci_patch_dependency_tables_with_leakage()
5204 								  &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);  in ci_patch_dependency_tables_with_leakage()
5206 								   &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);  in ci_patch_dependency_tables_with_leakage()
5208 								      &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);  in ci_patch_dependency_tables_with_leakage()
5210 								      &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);  in ci_patch_dependency_tables_with_leakage()
5212 								  &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);  in ci_patch_dependency_tables_with_leakage()
5214 								  &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);  in ci_patch_dependency_tables_with_leakage()
5216 							       &adev->pm.dpm.dyn_state.phase_shedding_limits_table);  in ci_patch_dependency_tables_with_leakage()
5218 							&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);  in ci_patch_dependency_tables_with_leakage()
5220 							&adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);  in ci_patch_dependency_tables_with_leakage()
5222 						     &adev->pm.dpm.dyn_state.cac_leakage_table);  in ci_patch_dependency_tables_with_leakage()
5251 	struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;  in ci_dpm_pre_set_power_state()
5280 	struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;  in ci_dpm_enable()
5410 		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,  in ci_dpm_enable()
5412 		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,  in ci_dpm_enable()
5429 	struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;  in ci_dpm_disable()
5431 	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,  in ci_dpm_disable()
5433 	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,  in ci_dpm_disable()
5580 		adev->pm.dpm.boot_ps = rps;  in ci_parse_pplib_non_clock_info()
5582 		adev->pm.dpm.uvd_ps = rps;  in ci_parse_pplib_non_clock_info()
5688 	adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *  in ci_parse_power_table()
5690 	if (!adev->pm.dpm.ps)  in ci_parse_power_table()
5701 			kfree(adev->pm.dpm.ps);  in ci_parse_power_table()
5704 		adev->pm.dpm.ps[i].ps_priv = ps;  in ci_parse_power_table()
5705 		ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],  in ci_parse_power_table()
5720 						  &adev->pm.dpm.ps[i], k,  in ci_parse_power_table()
5726 	adev->pm.dpm.num_ps = state_array->ucNumEntries;  in ci_parse_power_table()
5731 		clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;  in ci_parse_power_table()
5738 		adev->pm.dpm.vce_states[i].sclk = sclk;  in ci_parse_power_table()
5739 		adev->pm.dpm.vce_states[i].mclk = mclk;  in ci_parse_power_table()
5776 	for (i = 0; i < adev->pm.dpm.num_ps; i++) {  in ci_dpm_fini()
5777 		kfree(adev->pm.dpm.ps[i].ps_priv);  in ci_dpm_fini()
5779 	kfree(adev->pm.dpm.ps);  in ci_dpm_fini()
5780 	kfree(adev->pm.dpm.priv);  in ci_dpm_fini()
5781 	kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);  in ci_dpm_fini()
5845 	adev->pm.dpm.priv = pi;  in ci_dpm_init()
5927 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =  in ci_dpm_init()
5929 	if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {  in ci_dpm_init()
5933 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;  in ci_dpm_init()
5934 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;  in ci_dpm_init()
5935 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;  in ci_dpm_init()
5936 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;  in ci_dpm_init()
5937 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;  in ci_dpm_init()
5938 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;  in ci_dpm_init()
5939 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;  in ci_dpm_init()
5940 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;  in ci_dpm_init()
5941 	adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;  in ci_dpm_init()
5943 	adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;  in ci_dpm_init()
5944 	adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;  in ci_dpm_init()
5945 	adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;  in ci_dpm_init()
5947 	adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;  in ci_dpm_init()
5948 	adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;  in ci_dpm_init()
5949 	adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;  in ci_dpm_init()
5950 	adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;  in ci_dpm_init()
5969 		adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;  in ci_dpm_init()
5972 		adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;  in ci_dpm_init()
5978 		adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;  in ci_dpm_init()
5981 		adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;  in ci_dpm_init()
6021 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {  in ci_dpm_init()
6027 			adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;  in ci_dpm_init()
6030 	if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {  in ci_dpm_init()
6036 			adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;  in ci_dpm_init()
6069 	if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||  in ci_dpm_init()
6070 	    (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))  in ci_dpm_init()
6071 		adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =  in ci_dpm_init()
6072 			adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;  in ci_dpm_init()
6207 	ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);  in ci_dpm_sw_init()
6211 	ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);  in ci_dpm_sw_init()
6216 	adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;  in ci_dpm_sw_init()
6217 	adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;  in ci_dpm_sw_init()
6218 	adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;  in ci_dpm_sw_init()
6232 	INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);  in ci_dpm_sw_init()
6237 	adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;  in ci_dpm_sw_init()
6307 		adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;  in ci_dpm_suspend()
6620 		adev->pm.dpm.thermal.high_to_low = false;  in ci_dpm_process_interrupt()
6625 		adev->pm.dpm.thermal.high_to_low = true;  in ci_dpm_process_interrupt()
6633 		schedule_work(&adev->pm.dpm.thermal.work);  in ci_dpm_process_interrupt()
6699 	adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;  in ci_dpm_set_irq_funcs()
6700 	adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;  in ci_dpm_set_irq_funcs()