Lines Matching refs:adev
184 static u8 ci_get_memory_module_index(struct amdgpu_device *adev) in ci_get_memory_module_index() argument
194 static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev, in ci_copy_and_switch_arb_sets() argument
279 static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, in ci_trim_voltage_table_to_fit_state_table() argument
296 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
299 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
300 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
302 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
303 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
304 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
306 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
308 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
309 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
311 static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev) in ci_get_pi() argument
313 struct ci_power_info *pi = adev->pm.dpm.priv; in ci_get_pi()
325 static void ci_initialize_powertune_defaults(struct amdgpu_device *adev) in ci_initialize_powertune_defaults() argument
327 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_powertune_defaults()
329 switch (adev->pdev->device) { in ci_initialize_powertune_defaults()
376 if (adev->asic_type == CHIP_HAWAII) in ci_initialize_powertune_defaults()
390 static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev) in ci_populate_bapm_vddc_vid_sidd() argument
392 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_vddc_vid_sidd()
398 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
400 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
402 if (adev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
403 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
406 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
407 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
408 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
409 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
410 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
412 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
413 hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
419 static int ci_populate_vddc_vid(struct amdgpu_device *adev) in ci_populate_vddc_vid() argument
421 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_vddc_vid()
434 static int ci_populate_svi_load_line(struct amdgpu_device *adev) in ci_populate_svi_load_line() argument
436 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_svi_load_line()
447 static int ci_populate_tdc_limit(struct amdgpu_device *adev) in ci_populate_tdc_limit() argument
449 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_tdc_limit()
453 tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
462 static int ci_populate_dw8(struct amdgpu_device *adev) in ci_populate_dw8() argument
464 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_dw8()
468 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_populate_dw8()
482 static int ci_populate_fuzzy_fan(struct amdgpu_device *adev) in ci_populate_fuzzy_fan() argument
484 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_fuzzy_fan()
486 if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
487 (adev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
488 adev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
489 adev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
492 cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
497 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev) in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() argument
499 struct ci_power_info *pi = ci_get_pi(adev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
529 static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev) in ci_populate_bapm_vddc_base_leakage_sidd() argument
531 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_vddc_base_leakage_sidd()
535 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
546 static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev) in ci_populate_bapm_parameters_in_dpm_table() argument
548 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_bapm_parameters_in_dpm_table()
552 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
553 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
594 static int ci_populate_pm_base(struct amdgpu_device *adev) in ci_populate_pm_base() argument
596 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_pm_base()
601 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_populate_pm_base()
607 ret = ci_populate_bapm_vddc_vid_sidd(adev); in ci_populate_pm_base()
610 ret = ci_populate_vddc_vid(adev); in ci_populate_pm_base()
613 ret = ci_populate_svi_load_line(adev); in ci_populate_pm_base()
616 ret = ci_populate_tdc_limit(adev); in ci_populate_pm_base()
619 ret = ci_populate_dw8(adev); in ci_populate_pm_base()
622 ret = ci_populate_fuzzy_fan(adev); in ci_populate_pm_base()
625 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev); in ci_populate_pm_base()
628 ret = ci_populate_bapm_vddc_base_leakage_sidd(adev); in ci_populate_pm_base()
631 ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset, in ci_populate_pm_base()
641 static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable) in ci_do_enable_didt() argument
643 struct ci_power_info *pi = ci_get_pi(adev); in ci_do_enable_didt()
683 static int ci_program_pt_config_registers(struct amdgpu_device *adev, in ci_program_pt_config_registers() argument
731 static int ci_enable_didt(struct amdgpu_device *adev, bool enable) in ci_enable_didt() argument
733 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_didt()
738 gfx_v7_0_enter_rlc_safe_mode(adev); in ci_enable_didt()
741 ret = ci_program_pt_config_registers(adev, didt_config_ci); in ci_enable_didt()
743 gfx_v7_0_exit_rlc_safe_mode(adev); in ci_enable_didt()
748 ci_do_enable_didt(adev, enable); in ci_enable_didt()
750 gfx_v7_0_exit_rlc_safe_mode(adev); in ci_enable_didt()
756 static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable) in ci_enable_power_containment() argument
758 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_power_containment()
766 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); in ci_enable_power_containment()
774 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable); in ci_enable_power_containment()
782 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable); in ci_enable_power_containment()
787 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
793 ci_set_power_limit(adev, default_pwr_limit); in ci_enable_power_containment()
800 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable); in ci_enable_power_containment()
803 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); in ci_enable_power_containment()
806 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable); in ci_enable_power_containment()
814 static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable) in ci_enable_smc_cac() argument
816 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_smc_cac()
822 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); in ci_enable_smc_cac()
830 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); in ci_enable_smc_cac()
838 static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev, in ci_enable_thermal_based_sclk_dpm() argument
841 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_thermal_based_sclk_dpm()
846 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM); in ci_enable_thermal_based_sclk_dpm()
848 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM); in ci_enable_thermal_based_sclk_dpm()
857 static int ci_power_control_set_level(struct amdgpu_device *adev) in ci_power_control_set_level() argument
859 struct ci_power_info *pi = ci_get_pi(adev); in ci_power_control_set_level()
861 adev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
869 adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
873 ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp); in ci_power_control_set_level()
879 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) in ci_dpm_powergate_uvd() argument
881 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_powergate_uvd()
888 ci_update_uvd_dpm(adev, gate); in ci_dpm_powergate_uvd()
891 static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev) in ci_dpm_vblank_too_short() argument
893 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); in ci_dpm_vblank_too_short()
894 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; in ci_dpm_vblank_too_short()
903 static void ci_apply_state_adjust_rules(struct amdgpu_device *adev, in ci_apply_state_adjust_rules() argument
907 struct ci_power_info *pi = ci_get_pi(adev); in ci_apply_state_adjust_rules()
914 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
915 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
921 if ((adev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
922 ci_dpm_vblank_too_short(adev)) in ci_apply_state_adjust_rules()
932 if (adev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
933 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
935 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
937 if (adev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
957 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
958 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
959 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
960 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
978 static int ci_thermal_set_temperature_range(struct amdgpu_device *adev, in ci_thermal_set_temperature_range() argument
1008 adev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
1009 adev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
1013 static int ci_thermal_enable_alert(struct amdgpu_device *adev, in ci_thermal_enable_alert() argument
1023 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable); in ci_thermal_enable_alert()
1032 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable); in ci_thermal_enable_alert()
1042 static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) in ci_fan_ctrl_set_static_mode() argument
1044 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_set_static_mode()
1066 static int ci_thermal_setup_fan_table(struct amdgpu_device *adev) in ci_thermal_setup_fan_table() argument
1068 struct ci_power_info *pi = ci_get_pi(adev); in ci_thermal_setup_fan_table()
1078 adev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1086 adev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1090 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
1094 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
1095 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
1097 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
1098 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
1103 fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
1104 fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
1105 fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
1112 fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
1120 reference_clock = amdgpu_asic_get_xclk(adev); in ci_thermal_setup_fan_table()
1122 fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
1131 ret = amdgpu_ci_copy_bytes_to_smc(adev, in ci_thermal_setup_fan_table()
1139 adev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1145 static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) in ci_fan_ctrl_start_smc_fan_control() argument
1147 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_start_smc_fan_control()
1151 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_fan_ctrl_start_smc_fan_control()
1156 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_fan_ctrl_start_smc_fan_control()
1158 adev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1162 ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_fan_ctrl_start_smc_fan_control()
1174 static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) in ci_fan_ctrl_stop_smc_fan_control() argument
1177 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_stop_smc_fan_control()
1179 ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl); in ci_fan_ctrl_stop_smc_fan_control()
1188 static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev, in ci_dpm_get_fan_speed_percent() argument
1194 if (adev->pm.no_fan) in ci_dpm_get_fan_speed_percent()
1215 static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev, in ci_dpm_set_fan_speed_percent() argument
1221 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_fan_speed_percent()
1223 if (adev->pm.no_fan) in ci_dpm_set_fan_speed_percent()
1249 static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode) in ci_dpm_set_fan_control_mode() argument
1253 if (adev->pm.dpm.fan.ucode_fan_control) in ci_dpm_set_fan_control_mode()
1254 ci_fan_ctrl_stop_smc_fan_control(adev); in ci_dpm_set_fan_control_mode()
1255 ci_fan_ctrl_set_static_mode(adev, mode); in ci_dpm_set_fan_control_mode()
1258 if (adev->pm.dpm.fan.ucode_fan_control) in ci_dpm_set_fan_control_mode()
1259 ci_thermal_start_smc_fan_control(adev); in ci_dpm_set_fan_control_mode()
1261 ci_fan_ctrl_set_default_mode(adev); in ci_dpm_set_fan_control_mode()
1265 static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev) in ci_dpm_get_fan_control_mode() argument
1267 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_fan_control_mode()
1278 static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
1282 u32 xclk = amdgpu_asic_get_xclk(adev);
1284 if (adev->pm.no_fan)
1287 if (adev->pm.fan_pulses_per_revolution == 0)
1300 static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
1304 u32 xclk = amdgpu_asic_get_xclk(adev);
1306 if (adev->pm.no_fan)
1309 if (adev->pm.fan_pulses_per_revolution == 0)
1312 if ((speed < adev->pm.fan_min_rpm) ||
1313 (speed > adev->pm.fan_max_rpm))
1316 if (adev->pm.dpm.fan.ucode_fan_control)
1317 ci_fan_ctrl_stop_smc_fan_control(adev);
1324 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
1330 static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev) in ci_fan_ctrl_set_default_mode() argument
1332 struct ci_power_info *pi = ci_get_pi(adev); in ci_fan_ctrl_set_default_mode()
1347 static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev) in ci_thermal_start_smc_fan_control() argument
1349 if (adev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1350 ci_fan_ctrl_start_smc_fan_control(adev); in ci_thermal_start_smc_fan_control()
1351 ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); in ci_thermal_start_smc_fan_control()
1355 static void ci_thermal_initialize(struct amdgpu_device *adev) in ci_thermal_initialize() argument
1359 if (adev->pm.fan_pulses_per_revolution) { in ci_thermal_initialize()
1361 tmp |= (adev->pm.fan_pulses_per_revolution - 1) in ci_thermal_initialize()
1371 static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev) in ci_thermal_start_thermal_controller() argument
1375 ci_thermal_initialize(adev); in ci_thermal_start_thermal_controller()
1376 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX); in ci_thermal_start_thermal_controller()
1379 ret = ci_thermal_enable_alert(adev, true); in ci_thermal_start_thermal_controller()
1382 if (adev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1383 ret = ci_thermal_setup_fan_table(adev); in ci_thermal_start_thermal_controller()
1386 ci_thermal_start_smc_fan_control(adev); in ci_thermal_start_thermal_controller()
1392 static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev) in ci_thermal_stop_thermal_controller() argument
1394 if (!adev->pm.no_fan) in ci_thermal_stop_thermal_controller()
1395 ci_fan_ctrl_set_default_mode(adev); in ci_thermal_stop_thermal_controller()
1399 static int ci_read_smc_soft_register(struct amdgpu_device *adev,
1402 struct ci_power_info *pi = ci_get_pi(adev);
1404 return amdgpu_ci_read_smc_sram_dword(adev,
1410 static int ci_write_smc_soft_register(struct amdgpu_device *adev, in ci_write_smc_soft_register() argument
1413 struct ci_power_info *pi = ci_get_pi(adev); in ci_write_smc_soft_register()
1415 return amdgpu_ci_write_smc_sram_dword(adev, in ci_write_smc_soft_register()
1420 static void ci_init_fps_limits(struct amdgpu_device *adev) in ci_init_fps_limits() argument
1422 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_fps_limits()
1436 static int ci_update_sclk_t(struct amdgpu_device *adev) in ci_update_sclk_t() argument
1438 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_sclk_t()
1445 ret = amdgpu_ci_copy_bytes_to_smc(adev, in ci_update_sclk_t()
1456 static void ci_get_leakage_voltages(struct amdgpu_device *adev) in ci_get_leakage_voltages() argument
1458 struct ci_power_info *pi = ci_get_pi(adev); in ci_get_leakage_voltages()
1466 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1469 if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0) in ci_get_leakage_voltages()
1477 } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) { in ci_get_leakage_voltages()
1480 if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci, in ci_get_leakage_voltages()
1498 static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) in ci_set_dpm_event_sources() argument
1500 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_dpm_event_sources()
1547 static void ci_enable_auto_throttle_source(struct amdgpu_device *adev, in ci_enable_auto_throttle_source() argument
1551 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_auto_throttle_source()
1556 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1561 ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1566 static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev) in ci_enable_vr_hot_gpio_interrupt() argument
1568 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1569 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt); in ci_enable_vr_hot_gpio_interrupt()
1572 static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev) in ci_unfreeze_sclk_mclk_dpm() argument
1574 struct ci_power_info *pi = ci_get_pi(adev); in ci_unfreeze_sclk_mclk_dpm()
1582 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); in ci_unfreeze_sclk_mclk_dpm()
1589 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); in ci_unfreeze_sclk_mclk_dpm()
1598 static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable) in ci_enable_sclk_mclk_dpm() argument
1600 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_sclk_mclk_dpm()
1605 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable); in ci_enable_sclk_mclk_dpm()
1611 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable); in ci_enable_sclk_mclk_dpm()
1630 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable); in ci_enable_sclk_mclk_dpm()
1636 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable); in ci_enable_sclk_mclk_dpm()
1645 static int ci_start_dpm(struct amdgpu_device *adev) in ci_start_dpm() argument
1647 struct ci_power_info *pi = ci_get_pi(adev); in ci_start_dpm()
1660 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); in ci_start_dpm()
1664 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable); in ci_start_dpm()
1668 ret = ci_enable_sclk_mclk_dpm(adev, true); in ci_start_dpm()
1673 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable); in ci_start_dpm()
1681 static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev) in ci_freeze_sclk_mclk_dpm() argument
1683 struct ci_power_info *pi = ci_get_pi(adev); in ci_freeze_sclk_mclk_dpm()
1691 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel); in ci_freeze_sclk_mclk_dpm()
1698 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel); in ci_freeze_sclk_mclk_dpm()
1706 static int ci_stop_dpm(struct amdgpu_device *adev) in ci_stop_dpm() argument
1708 struct ci_power_info *pi = ci_get_pi(adev); in ci_stop_dpm()
1722 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable); in ci_stop_dpm()
1727 ret = ci_enable_sclk_mclk_dpm(adev, false); in ci_stop_dpm()
1731 smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable); in ci_stop_dpm()
1738 static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable) in ci_enable_sclk_control() argument
1750 static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
1753 struct ci_power_info *pi = ci_get_pi(adev);
1755 adev->pm.dpm.dyn_state.cac_tdp_table;
1763 ci_set_power_limit(adev, power_limit);
1767 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
1769 amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
1776 static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, in amdgpu_ci_send_msg_to_smc_with_parameter() argument
1780 return amdgpu_ci_send_msg_to_smc(adev, msg); in amdgpu_ci_send_msg_to_smc_with_parameter()
1783 static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev, in amdgpu_ci_send_msg_to_smc_return_parameter() argument
1788 smc_result = amdgpu_ci_send_msg_to_smc(adev, msg); in amdgpu_ci_send_msg_to_smc_return_parameter()
1796 static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n) in ci_dpm_force_state_sclk() argument
1798 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_sclk()
1802 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); in ci_dpm_force_state_sclk()
1810 static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n) in ci_dpm_force_state_mclk() argument
1812 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_mclk()
1816 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); in ci_dpm_force_state_mclk()
1824 static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n) in ci_dpm_force_state_pcie() argument
1826 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_state_pcie()
1830 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n); in ci_dpm_force_state_pcie()
1838 static int ci_set_power_limit(struct amdgpu_device *adev, u32 n) in ci_set_power_limit() argument
1840 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_power_limit()
1844 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n); in ci_set_power_limit()
1852 static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev, in ci_set_overdrive_target_tdp() argument
1856 amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); in ci_set_overdrive_target_tdp()
1863 static int ci_set_boot_state(struct amdgpu_device *adev)
1865 return ci_enable_sclk_mclk_dpm(adev, false);
1869 static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev) in ci_get_average_sclk_freq() argument
1873 amdgpu_ci_send_msg_to_smc_return_parameter(adev, in ci_get_average_sclk_freq()
1882 static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev) in ci_get_average_mclk_freq() argument
1886 amdgpu_ci_send_msg_to_smc_return_parameter(adev, in ci_get_average_mclk_freq()
1895 static void ci_dpm_start_smc(struct amdgpu_device *adev) in ci_dpm_start_smc() argument
1899 amdgpu_ci_program_jump_on_start(adev); in ci_dpm_start_smc()
1900 amdgpu_ci_start_smc_clock(adev); in ci_dpm_start_smc()
1901 amdgpu_ci_start_smc(adev); in ci_dpm_start_smc()
1902 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_start_smc()
1908 static void ci_dpm_stop_smc(struct amdgpu_device *adev) in ci_dpm_stop_smc() argument
1910 amdgpu_ci_reset_smc(adev); in ci_dpm_stop_smc()
1911 amdgpu_ci_stop_smc_clock(adev); in ci_dpm_stop_smc()
1914 static int ci_process_firmware_header(struct amdgpu_device *adev) in ci_process_firmware_header() argument
1916 struct ci_power_info *pi = ci_get_pi(adev); in ci_process_firmware_header()
1920 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_process_firmware_header()
1929 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_process_firmware_header()
1938 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_process_firmware_header()
1947 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_process_firmware_header()
1956 ret = amdgpu_ci_read_smc_sram_dword(adev, in ci_process_firmware_header()
1968 static void ci_read_clock_registers(struct amdgpu_device *adev) in ci_read_clock_registers() argument
1970 struct ci_power_info *pi = ci_get_pi(adev); in ci_read_clock_registers()
1995 static void ci_init_sclk_t(struct amdgpu_device *adev) in ci_init_sclk_t() argument
1997 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_sclk_t()
2002 static void ci_enable_thermal_protection(struct amdgpu_device *adev, in ci_enable_thermal_protection() argument
2014 static void ci_enable_acpi_power_management(struct amdgpu_device *adev) in ci_enable_acpi_power_management() argument
2024 static int ci_enter_ulp_state(struct amdgpu_device *adev)
2034 static int ci_exit_ulp_state(struct amdgpu_device *adev)
2042 for (i = 0; i < adev->usec_timeout; i++) {
2052 static int ci_notify_smc_display_change(struct amdgpu_device *adev, in ci_notify_smc_display_change() argument
2057 return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; in ci_notify_smc_display_change()
2060 static int ci_enable_ds_master_switch(struct amdgpu_device *adev, in ci_enable_ds_master_switch() argument
2063 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_ds_master_switch()
2067 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) in ci_enable_ds_master_switch()
2070 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) in ci_enable_ds_master_switch()
2075 if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) in ci_enable_ds_master_switch()
2083 static void ci_program_display_gap(struct amdgpu_device *adev) in ci_program_display_gap() argument
2088 u32 ref_clock = adev->clock.spll.reference_freq; in ci_program_display_gap()
2089 u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev); in ci_program_display_gap()
2090 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); in ci_program_display_gap()
2093 if (adev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
2109 ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); in ci_program_display_gap()
2110 …ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - … in ci_program_display_gap()
2113 ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
2117 static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) in ci_enable_spread_spectrum() argument
2119 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_spread_spectrum()
2139 static void ci_program_sstp(struct amdgpu_device *adev) in ci_program_sstp() argument
2146 static void ci_enable_display_gap(struct amdgpu_device *adev) in ci_enable_display_gap() argument
2158 static void ci_program_vc(struct amdgpu_device *adev) in ci_program_vc() argument
2176 static void ci_clear_vc(struct amdgpu_device *adev) in ci_clear_vc() argument
2194 static int ci_upload_firmware(struct amdgpu_device *adev) in ci_upload_firmware() argument
2196 struct ci_power_info *pi = ci_get_pi(adev); in ci_upload_firmware()
2199 for (i = 0; i < adev->usec_timeout; i++) { in ci_upload_firmware()
2205 amdgpu_ci_stop_smc_clock(adev); in ci_upload_firmware()
2206 amdgpu_ci_reset_smc(adev); in ci_upload_firmware()
2208 ret = amdgpu_ci_load_smc_ucode(adev, pi->sram_end); in ci_upload_firmware()
2214 static int ci_get_svi2_voltage_table(struct amdgpu_device *adev, in ci_get_svi2_voltage_table() argument
2235 static int ci_construct_voltage_tables(struct amdgpu_device *adev) in ci_construct_voltage_tables() argument
2237 struct ci_power_info *pi = ci_get_pi(adev); in ci_construct_voltage_tables()
2241 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, in ci_construct_voltage_tables()
2247 ret = ci_get_svi2_voltage_table(adev, in ci_construct_voltage_tables()
2248 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2255 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC, in ci_construct_voltage_tables()
2259 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, in ci_construct_voltage_tables()
2265 ret = ci_get_svi2_voltage_table(adev, in ci_construct_voltage_tables()
2266 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2273 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI, in ci_construct_voltage_tables()
2277 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, in ci_construct_voltage_tables()
2283 ret = ci_get_svi2_voltage_table(adev, in ci_construct_voltage_tables()
2284 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2291 ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD, in ci_construct_voltage_tables()
2297 static void ci_populate_smc_voltage_table(struct amdgpu_device *adev, in ci_populate_smc_voltage_table() argument
2303 ret = ci_get_std_voltage_value_sidd(adev, voltage_table, in ci_populate_smc_voltage_table()
2319 static int ci_populate_smc_vddc_table(struct amdgpu_device *adev, in ci_populate_smc_vddc_table() argument
2322 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_vddc_table()
2327 ci_populate_smc_voltage_table(adev, in ci_populate_smc_vddc_table()
2342 static int ci_populate_smc_vddci_table(struct amdgpu_device *adev, in ci_populate_smc_vddci_table() argument
2346 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_vddci_table()
2350 ci_populate_smc_voltage_table(adev, in ci_populate_smc_vddci_table()
2365 static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev, in ci_populate_smc_mvdd_table() argument
2368 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_mvdd_table()
2373 ci_populate_smc_voltage_table(adev, in ci_populate_smc_mvdd_table()
2388 static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev, in ci_populate_smc_voltage_tables() argument
2393 ret = ci_populate_smc_vddc_table(adev, table); in ci_populate_smc_voltage_tables()
2397 ret = ci_populate_smc_vddci_table(adev, table); in ci_populate_smc_voltage_tables()
2401 ret = ci_populate_smc_mvdd_table(adev, table); in ci_populate_smc_voltage_tables()
2408 static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, in ci_populate_mvdd_value() argument
2411 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_mvdd_value()
2415 for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2416 if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2422 if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2429 static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev, in ci_get_std_voltage_value_sidd() argument
2438 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2441 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2442 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2444 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2446 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2449 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2451 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2453 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2459 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2461 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2463 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2466 idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2468 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2470 adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2480 static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev, in ci_populate_phase_value_based_on_sclk() argument
2497 static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev, in ci_populate_phase_value_based_on_mclk() argument
2514 static int ci_init_arb_table_index(struct amdgpu_device *adev) in ci_init_arb_table_index() argument
2516 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_arb_table_index()
2520 ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start, in ci_init_arb_table_index()
2528 return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start, in ci_init_arb_table_index()
2532 static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev, in ci_get_dependency_volt_by_clk() argument
2553 static u8 ci_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, in ci_get_sleep_divider_id_from_clock() argument
2573 static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) in ci_initial_switch_from_arb_f0_to_f1() argument
2575 return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); in ci_initial_switch_from_arb_f0_to_f1()
2578 static int ci_reset_to_default(struct amdgpu_device *adev) in ci_reset_to_default() argument
2580 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? in ci_reset_to_default()
2584 static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev) in ci_force_switch_to_arb_f0() argument
2593 return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); in ci_force_switch_to_arb_f0()
2596 static void ci_register_patching_mc_arb(struct amdgpu_device *adev, in ci_register_patching_mc_arb() argument
2608 ((adev->pdev->device == 0x67B0) || in ci_register_patching_mc_arb()
2609 (adev->pdev->device == 0x67B1))) { in ci_register_patching_mc_arb()
2622 static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev, in ci_populate_memory_timing_parameters() argument
2631 amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk); in ci_populate_memory_timing_parameters()
2637 ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2); in ci_populate_memory_timing_parameters()
2646 static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev) in ci_do_program_memory_timing_parameters() argument
2648 struct ci_power_info *pi = ci_get_pi(adev); in ci_do_program_memory_timing_parameters()
2657 ret = ci_populate_memory_timing_parameters(adev, in ci_do_program_memory_timing_parameters()
2667 ret = amdgpu_ci_copy_bytes_to_smc(adev, in ci_do_program_memory_timing_parameters()
2676 static int ci_program_memory_timing_parameters(struct amdgpu_device *adev) in ci_program_memory_timing_parameters() argument
2678 struct ci_power_info *pi = ci_get_pi(adev); in ci_program_memory_timing_parameters()
2683 return ci_do_program_memory_timing_parameters(adev); in ci_program_memory_timing_parameters()
2686 static void ci_populate_smc_initial_state(struct amdgpu_device *adev, in ci_populate_smc_initial_state() argument
2690 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_initial_state()
2693 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2694 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2701 for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2702 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2726 static void ci_populate_smc_link_level(struct amdgpu_device *adev, in ci_populate_smc_link_level() argument
2729 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_link_level()
2748 static int ci_populate_smc_uvd_level(struct amdgpu_device *adev, in ci_populate_smc_uvd_level() argument
2756 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2760 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2762 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2764 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2767 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_populate_smc_uvd_level()
2775 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_populate_smc_uvd_level()
2791 static int ci_populate_smc_vce_level(struct amdgpu_device *adev, in ci_populate_smc_vce_level() argument
2799 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2803 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2805 (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2808 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_populate_smc_vce_level()
2824 static int ci_populate_smc_acp_level(struct amdgpu_device *adev, in ci_populate_smc_acp_level() argument
2832 (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2836 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2838 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2841 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_populate_smc_acp_level()
2856 static int ci_populate_smc_samu_level(struct amdgpu_device *adev, in ci_populate_smc_samu_level() argument
2864 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2868 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2870 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2873 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_populate_smc_samu_level()
2888 static int ci_calculate_mclk_params(struct amdgpu_device *adev, in ci_calculate_mclk_params() argument
2894 struct ci_power_info *pi = ci_get_pi(adev); in ci_calculate_mclk_params()
2907 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2923 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { in ci_calculate_mclk_params()
2934 u32 reference_clock = adev->clock.mpll.reference_freq; in ci_calculate_mclk_params()
2943 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, in ci_calculate_mclk_params()
2980 static int ci_populate_single_memory_level(struct amdgpu_device *adev, in ci_populate_single_memory_level() argument
2984 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_single_memory_level()
2988 if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2989 ret = ci_get_dependency_volt_by_clk(adev, in ci_populate_single_memory_level()
2990 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2996 if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2997 ret = ci_get_dependency_volt_by_clk(adev, in ci_populate_single_memory_level()
2998 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
3004 if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
3005 ret = ci_get_dependency_volt_by_clk(adev, in ci_populate_single_memory_level()
3006 &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
3015 ci_populate_phase_value_based_on_mclk(adev, in ci_populate_single_memory_level()
3016 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
3039 (adev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
3046 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { in ci_populate_single_memory_level()
3071 …ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s… in ci_populate_single_memory_level()
3095 static int ci_populate_smc_acpi_level(struct amdgpu_device *adev, in ci_populate_smc_acpi_level() argument
3098 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_smc_acpi_level()
3116 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3118 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_populate_smc_acpi_level()
3167 if (ci_populate_mvdd_value(adev, 0, &voltage_level)) in ci_populate_smc_acpi_level()
3213 static int ci_enable_ulv(struct amdgpu_device *adev, bool enable) in ci_enable_ulv() argument
3215 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_ulv()
3220 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? in ci_enable_ulv()
3223 return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? in ci_enable_ulv()
3230 static int ci_populate_ulv_level(struct amdgpu_device *adev, in ci_populate_ulv_level() argument
3233 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_ulv_level()
3234 u16 ulv_voltage = adev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3245 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3249 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3251 if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3255 ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3267 static int ci_calculate_sclk_params(struct amdgpu_device *adev, in ci_calculate_sclk_params() argument
3271 struct ci_power_info *pi = ci_get_pi(adev); in ci_calculate_sclk_params()
3277 u32 reference_clock = adev->clock.spll.reference_freq; in ci_calculate_sclk_params()
3282 ret = amdgpu_atombios_get_clock_dividers(adev, in ci_calculate_sclk_params()
3299 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, in ci_calculate_sclk_params()
3323 static int ci_populate_single_graphic_level(struct amdgpu_device *adev, in ci_populate_single_graphic_level() argument
3328 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_single_graphic_level()
3331 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3335 ret = ci_get_dependency_volt_by_clk(adev, in ci_populate_single_graphic_level()
3336 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3347 ci_populate_phase_value_based_on_sclk(adev, in ci_populate_single_graphic_level()
3348 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3363 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(adev, in ci_populate_single_graphic_level()
3385 static int ci_populate_all_graphic_levels(struct amdgpu_device *adev) in ci_populate_all_graphic_levels() argument
3387 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_all_graphic_levels()
3399 ret = ci_populate_single_graphic_level(adev, in ci_populate_all_graphic_levels()
3416 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address, in ci_populate_all_graphic_levels()
3425 static int ci_populate_ulv_state(struct amdgpu_device *adev, in ci_populate_ulv_state() argument
3428 return ci_populate_ulv_level(adev, ulv_level); in ci_populate_ulv_state()
3431 static int ci_populate_all_memory_levels(struct amdgpu_device *adev) in ci_populate_all_memory_levels() argument
3433 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_all_memory_levels()
3447 ret = ci_populate_single_memory_level(adev, in ci_populate_all_memory_levels()
3455 ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) { in ci_populate_all_memory_levels()
3471 ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address, in ci_populate_all_memory_levels()
3480 static void ci_reset_single_dpm_table(struct amdgpu_device *adev, in ci_reset_single_dpm_table() argument
3499 static int ci_setup_default_pcie_tables(struct amdgpu_device *adev) in ci_setup_default_pcie_tables() argument
3501 struct ci_power_info *pi = ci_get_pi(adev); in ci_setup_default_pcie_tables()
3514 ci_reset_single_dpm_table(adev, in ci_setup_default_pcie_tables()
3518 if (adev->asic_type == CHIP_BONAIRE) in ci_setup_default_pcie_tables()
3547 static int ci_setup_default_dpm_tables(struct amdgpu_device *adev) in ci_setup_default_dpm_tables() argument
3549 struct ci_power_info *pi = ci_get_pi(adev); in ci_setup_default_dpm_tables()
3551 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3553 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3555 &adev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3569 ci_reset_single_dpm_table(adev, in ci_setup_default_dpm_tables()
3572 ci_reset_single_dpm_table(adev, in ci_setup_default_dpm_tables()
3575 ci_reset_single_dpm_table(adev, in ci_setup_default_dpm_tables()
3578 ci_reset_single_dpm_table(adev, in ci_setup_default_dpm_tables()
3581 ci_reset_single_dpm_table(adev, in ci_setup_default_dpm_tables()
3620 allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3630 allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3640 ci_setup_default_pcie_tables(adev); in ci_setup_default_dpm_tables()
3661 static int ci_init_smc_table(struct amdgpu_device *adev) in ci_init_smc_table() argument
3663 struct ci_power_info *pi = ci_get_pi(adev); in ci_init_smc_table()
3665 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; in ci_init_smc_table()
3669 ret = ci_setup_default_dpm_tables(adev); in ci_init_smc_table()
3674 ci_populate_smc_voltage_tables(adev, table); in ci_init_smc_table()
3676 ci_init_fps_limits(adev); in ci_init_smc_table()
3678 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3681 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3684 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) in ci_init_smc_table()
3688 ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3694 ret = ci_populate_all_graphic_levels(adev); in ci_init_smc_table()
3698 ret = ci_populate_all_memory_levels(adev); in ci_init_smc_table()
3702 ci_populate_smc_link_level(adev, table); in ci_init_smc_table()
3704 ret = ci_populate_smc_acpi_level(adev, table); in ci_init_smc_table()
3708 ret = ci_populate_smc_vce_level(adev, table); in ci_init_smc_table()
3712 ret = ci_populate_smc_acp_level(adev, table); in ci_init_smc_table()
3716 ret = ci_populate_smc_samu_level(adev, table); in ci_init_smc_table()
3720 ret = ci_do_program_memory_timing_parameters(adev); in ci_init_smc_table()
3724 ret = ci_populate_smc_uvd_level(adev, table); in ci_init_smc_table()
3747 ci_populate_smc_initial_state(adev, amdgpu_boot_state); in ci_init_smc_table()
3749 ret = ci_populate_bapm_parameters_in_dpm_table(adev); in ci_init_smc_table()
3797 ret = amdgpu_ci_copy_bytes_to_smc(adev, in ci_init_smc_table()
3809 static void ci_trim_single_dpm_states(struct amdgpu_device *adev, in ci_trim_single_dpm_states() argument
3824 static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev, in ci_trim_pcie_dpm_states() argument
3828 struct ci_power_info *pi = ci_get_pi(adev); in ci_trim_pcie_dpm_states()
3855 static int ci_trim_dpm_states(struct amdgpu_device *adev, in ci_trim_dpm_states() argument
3859 struct ci_power_info *pi = ci_get_pi(adev); in ci_trim_dpm_states()
3870 ci_trim_single_dpm_states(adev, in ci_trim_dpm_states()
3875 ci_trim_single_dpm_states(adev, in ci_trim_dpm_states()
3880 ci_trim_pcie_dpm_states(adev, in ci_trim_dpm_states()
3889 static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev) in ci_apply_disp_minimum_voltage_request() argument
3892 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3894 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3904 if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk) in ci_apply_disp_minimum_voltage_request()
3911 return (amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_apply_disp_minimum_voltage_request()
3921 static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev) in ci_upload_dpm_level_enable_mask() argument
3923 struct ci_power_info *pi = ci_get_pi(adev); in ci_upload_dpm_level_enable_mask()
3926 ci_apply_disp_minimum_voltage_request(adev); in ci_upload_dpm_level_enable_mask()
3930 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_upload_dpm_level_enable_mask()
3940 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_upload_dpm_level_enable_mask()
3951 result = amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_upload_dpm_level_enable_mask()
3963 static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev, in ci_find_dpm_states_clocks_in_dpm_table() argument
3966 struct ci_power_info *pi = ci_get_pi(adev); in ci_find_dpm_states_clocks_in_dpm_table()
3997 if (adev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
3998 adev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
4002 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev, in ci_populate_and_upload_sclk_mclk_dpm_levels() argument
4005 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_and_upload_sclk_mclk_dpm_levels()
4022 ret = ci_populate_all_graphic_levels(adev); in ci_populate_and_upload_sclk_mclk_dpm_levels()
4028 ret = ci_populate_all_memory_levels(adev); in ci_populate_and_upload_sclk_mclk_dpm_levels()
4036 static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) in ci_enable_uvd_dpm() argument
4038 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_uvd_dpm()
4042 if (adev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
4043 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
4045 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
4050 for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
4051 if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
4059 amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_enable_uvd_dpm()
4066 amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_enable_uvd_dpm()
4074 amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_enable_uvd_dpm()
4080 return (amdgpu_ci_send_msg_to_smc(adev, enable ? in ci_enable_uvd_dpm()
4085 static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable) in ci_enable_vce_dpm() argument
4087 struct ci_power_info *pi = ci_get_pi(adev); in ci_enable_vce_dpm()
4091 if (adev->pm.dpm.ac_power) in ci_enable_vce_dpm()
4092 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
4094 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
4098 for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
4099 if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
4107 amdgpu_ci_send_msg_to_smc_with_parameter(adev, in ci_enable_vce_dpm()
4112 return (amdgpu_ci_send_msg_to_smc(adev, enable ? in ci_enable_vce_dpm()
4118 static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
4120 struct ci_power_info *pi = ci_get_pi(adev);
4124 if (adev->pm.dpm.ac_power)
4125 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4127 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4131 for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4132 … if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4140 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4144 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4149 static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
4151 struct ci_power_info *pi = ci_get_pi(adev);
4155 if (adev->pm.dpm.ac_power)
4156 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4158 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4162 for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4163 if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4171 amdgpu_ci_send_msg_to_smc_with_parameter(adev,
4176 return (amdgpu_ci_send_msg_to_smc(adev, enable ?
4182 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in ci_update_uvd_dpm() argument
4184 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_uvd_dpm()
4189 (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4193 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4201 return ci_enable_uvd_dpm(adev, !gate); in ci_update_uvd_dpm()
4204 static u8 ci_get_vce_boot_level(struct amdgpu_device *adev) in ci_get_vce_boot_level() argument
4209 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4219 static int ci_update_vce_dpm(struct amdgpu_device *adev, in ci_update_vce_dpm() argument
4223 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_vce_dpm()
4230 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in ci_update_vce_dpm()
4235 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev); in ci_update_vce_dpm()
4241 ret = ci_enable_vce_dpm(adev, true); in ci_update_vce_dpm()
4244 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in ci_update_vce_dpm()
4249 ret = ci_enable_vce_dpm(adev, false); in ci_update_vce_dpm()
4256 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4258 return ci_enable_samu_dpm(adev, gate);
4261 static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
4263 struct ci_power_info *pi = ci_get_pi(adev);
4275 return ci_enable_acp_dpm(adev, !gate);
4279 static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev, in ci_generate_dpm_level_enable_mask() argument
4282 struct ci_power_info *pi = ci_get_pi(adev); in ci_generate_dpm_level_enable_mask()
4285 ret = ci_trim_dpm_states(adev, amdgpu_state); in ci_generate_dpm_level_enable_mask()
4305 static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev, in ci_get_lowest_enabled_level() argument
4317 static int ci_dpm_force_performance_level(struct amdgpu_device *adev, in ci_dpm_force_performance_level() argument
4320 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_force_performance_level()
4332 ret = ci_dpm_force_state_pcie(adev, level); in ci_dpm_force_performance_level()
4335 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4352 ret = ci_dpm_force_state_sclk(adev, levels); in ci_dpm_force_performance_level()
4355 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4372 ret = ci_dpm_force_state_mclk(adev, levels); in ci_dpm_force_performance_level()
4375 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4392 ret = ci_dpm_force_state_pcie(adev, level); in ci_dpm_force_performance_level()
4395 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4408 levels = ci_get_lowest_enabled_level(adev, in ci_dpm_force_performance_level()
4410 ret = ci_dpm_force_state_sclk(adev, levels); in ci_dpm_force_performance_level()
4413 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4424 levels = ci_get_lowest_enabled_level(adev, in ci_dpm_force_performance_level()
4426 ret = ci_dpm_force_state_mclk(adev, levels); in ci_dpm_force_performance_level()
4429 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4440 levels = ci_get_lowest_enabled_level(adev, in ci_dpm_force_performance_level()
4442 ret = ci_dpm_force_state_pcie(adev, levels); in ci_dpm_force_performance_level()
4445 for (i = 0; i < adev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4458 smc_result = amdgpu_ci_send_msg_to_smc(adev, in ci_dpm_force_performance_level()
4463 ret = ci_upload_dpm_level_enable_mask(adev); in ci_dpm_force_performance_level()
4468 adev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
4473 static int ci_set_mc_special_registers(struct amdgpu_device *adev, in ci_set_mc_special_registers() argument
4501 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) in ci_set_mc_special_registers()
4508 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { in ci_set_mc_special_registers()
4670 static int ci_register_patching_mc_seq(struct amdgpu_device *adev, in ci_register_patching_mc_seq() argument
4681 ((adev->pdev->device == 0x67B0) || in ci_register_patching_mc_seq()
4682 (adev->pdev->device == 0x67B1))) { in ci_register_patching_mc_seq()
4760 static int ci_initialize_mc_reg_table(struct amdgpu_device *adev) in ci_initialize_mc_reg_table() argument
4762 struct ci_power_info *pi = ci_get_pi(adev); in ci_initialize_mc_reg_table()
4765 u8 module_index = ci_get_memory_module_index(adev); in ci_initialize_mc_reg_table()
4793 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); in ci_initialize_mc_reg_table()
4803 ret = ci_register_patching_mc_seq(adev, ci_table); in ci_initialize_mc_reg_table()
4807 ret = ci_set_mc_special_registers(adev, ci_table); in ci_initialize_mc_reg_table()
4819 static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev, in ci_populate_mc_reg_addresses() argument
4822 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_mc_reg_addresses()
4854 static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, in ci_convert_mc_reg_table_entry_to_smc() argument
4858 struct ci_power_info *pi = ci_get_pi(adev); in ci_convert_mc_reg_table_entry_to_smc()
4874 static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, in ci_convert_mc_reg_table_to_smc() argument
4877 struct ci_power_info *pi = ci_get_pi(adev); in ci_convert_mc_reg_table_to_smc()
4881 ci_convert_mc_reg_table_entry_to_smc(adev, in ci_convert_mc_reg_table_to_smc()
4886 static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev) in ci_populate_initial_mc_reg_table() argument
4888 struct ci_power_info *pi = ci_get_pi(adev); in ci_populate_initial_mc_reg_table()
4893 ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4896 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4898 return amdgpu_ci_copy_bytes_to_smc(adev, in ci_populate_initial_mc_reg_table()
4905 static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev) in ci_update_and_upload_mc_reg_table() argument
4907 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_and_upload_mc_reg_table()
4914 ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4916 return amdgpu_ci_copy_bytes_to_smc(adev, in ci_update_and_upload_mc_reg_table()
4925 static void ci_enable_voltage_control(struct amdgpu_device *adev) in ci_enable_voltage_control() argument
4933 static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev, in ci_get_maximum_link_speed() argument
4949 static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev) in ci_get_current_pcie_speed() argument
4960 static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev) in ci_get_current_pcie_lane_number() argument
4984 static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev, in ci_request_link_speed_change_before_state_change() argument
4988 struct ci_power_info *pi = ci_get_pi(adev); in ci_request_link_speed_change_before_state_change()
4990 ci_get_maximum_link_speed(adev, amdgpu_new_state); in ci_request_link_speed_change_before_state_change()
4994 current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state); in ci_request_link_speed_change_before_state_change()
5004 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in ci_request_link_speed_change_before_state_change()
5010 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in ci_request_link_speed_change_before_state_change()
5014 pi->force_pcie_gen = ci_get_current_pcie_speed(adev); in ci_request_link_speed_change_before_state_change()
5023 static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, in ci_notify_link_speed_change_after_state_change() argument
5027 struct ci_power_info *pi = ci_get_pi(adev); in ci_notify_link_speed_change_after_state_change()
5029 ci_get_maximum_link_speed(adev, amdgpu_new_state); in ci_notify_link_speed_change_after_state_change()
5041 (ci_get_current_pcie_speed(adev) > 0)) in ci_notify_link_speed_change_after_state_change()
5045 amdgpu_acpi_pcie_performance_request(adev, request, false); in ci_notify_link_speed_change_after_state_change()
5050 static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev) in ci_set_private_data_variables_based_on_pptable() argument
5052 struct ci_power_info *pi = ci_get_pi(adev); in ci_set_private_data_variables_based_on_pptable()
5054 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
5056 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
5058 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
5081 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
5083 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
5085 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
5087 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
5093 static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc) in ci_patch_with_vddc_leakage() argument
5095 struct ci_power_info *pi = ci_get_pi(adev); in ci_patch_with_vddc_leakage()
5107 static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci) in ci_patch_with_vddci_leakage() argument
5109 struct ci_power_info *pi = ci_get_pi(adev); in ci_patch_with_vddci_leakage()
5121 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev, in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
5128 ci_patch_with_vddc_leakage(adev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
5132 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev, in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
5139 ci_patch_with_vddci_leakage(adev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
5143 …atic void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev, in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
5150 ci_patch_with_vddc_leakage(adev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
5154 …atic void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev, in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
5161 ci_patch_with_vddc_leakage(adev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
5165 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev, in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
5172 ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5176 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev, in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
5180 ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5181 ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5185 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev, in ci_patch_cac_leakage_table_with_vddc_leakage() argument
5192 ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()
5196 static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev) in ci_patch_dependency_tables_with_leakage() argument
5199 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5200 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5201 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5202 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5203 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5204 &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5205 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5206 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5207 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5208 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5209 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5210 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5211 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5212 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5213 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5214 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5215 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5216 &adev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5217 ci_patch_clock_voltage_limits_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5218 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5219 ci_patch_clock_voltage_limits_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5220 &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5221 ci_patch_cac_leakage_table_with_vddc_leakage(adev, in ci_patch_dependency_tables_with_leakage()
5222 &adev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5226 static void ci_update_current_ps(struct amdgpu_device *adev, in ci_update_current_ps() argument
5230 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_current_ps()
5237 static void ci_update_requested_ps(struct amdgpu_device *adev, in ci_update_requested_ps() argument
5241 struct ci_power_info *pi = ci_get_pi(adev); in ci_update_requested_ps()
5248 static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev) in ci_dpm_pre_set_power_state() argument
5250 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_pre_set_power_state()
5251 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5254 ci_update_requested_ps(adev, new_ps); in ci_dpm_pre_set_power_state()
5256 ci_apply_state_adjust_rules(adev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5261 static void ci_dpm_post_set_power_state(struct amdgpu_device *adev) in ci_dpm_post_set_power_state() argument
5263 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_post_set_power_state()
5266 ci_update_current_ps(adev, new_ps); in ci_dpm_post_set_power_state()
5270 static void ci_dpm_setup_asic(struct amdgpu_device *adev) in ci_dpm_setup_asic() argument
5272 ci_read_clock_registers(adev); in ci_dpm_setup_asic()
5273 ci_enable_acpi_power_management(adev); in ci_dpm_setup_asic()
5274 ci_init_sclk_t(adev); in ci_dpm_setup_asic()
5277 static int ci_dpm_enable(struct amdgpu_device *adev) in ci_dpm_enable() argument
5279 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_enable()
5280 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in ci_dpm_enable()
5283 if (amdgpu_ci_is_smc_running(adev)) in ci_dpm_enable()
5286 ci_enable_voltage_control(adev); in ci_dpm_enable()
5287 ret = ci_construct_voltage_tables(adev); in ci_dpm_enable()
5294 ret = ci_initialize_mc_reg_table(adev); in ci_dpm_enable()
5299 ci_enable_spread_spectrum(adev, true); in ci_dpm_enable()
5301 ci_enable_thermal_protection(adev, true); in ci_dpm_enable()
5302 ci_program_sstp(adev); in ci_dpm_enable()
5303 ci_enable_display_gap(adev); in ci_dpm_enable()
5304 ci_program_vc(adev); in ci_dpm_enable()
5305 ret = ci_upload_firmware(adev); in ci_dpm_enable()
5310 ret = ci_process_firmware_header(adev); in ci_dpm_enable()
5315 ret = ci_initial_switch_from_arb_f0_to_f1(adev); in ci_dpm_enable()
5320 ret = ci_init_smc_table(adev); in ci_dpm_enable()
5325 ret = ci_init_arb_table_index(adev); in ci_dpm_enable()
5331 ret = ci_populate_initial_mc_reg_table(adev); in ci_dpm_enable()
5337 ret = ci_populate_pm_base(adev); in ci_dpm_enable()
5342 ci_dpm_start_smc(adev); in ci_dpm_enable()
5343 ci_enable_vr_hot_gpio_interrupt(adev); in ci_dpm_enable()
5344 ret = ci_notify_smc_display_change(adev, false); in ci_dpm_enable()
5349 ci_enable_sclk_control(adev, true); in ci_dpm_enable()
5350 ret = ci_enable_ulv(adev, true); in ci_dpm_enable()
5355 ret = ci_enable_ds_master_switch(adev, true); in ci_dpm_enable()
5360 ret = ci_start_dpm(adev); in ci_dpm_enable()
5365 ret = ci_enable_didt(adev, true); in ci_dpm_enable()
5370 ret = ci_enable_smc_cac(adev, true); in ci_dpm_enable()
5375 ret = ci_enable_power_containment(adev, true); in ci_dpm_enable()
5381 ret = ci_power_control_set_level(adev); in ci_dpm_enable()
5387 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in ci_dpm_enable()
5389 ret = ci_enable_thermal_based_sclk_dpm(adev, true); in ci_dpm_enable()
5395 ci_thermal_start_thermal_controller(adev); in ci_dpm_enable()
5397 ci_update_current_ps(adev, boot_ps); in ci_dpm_enable()
5399 if (adev->irq.installed && in ci_dpm_enable()
5400 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { in ci_dpm_enable()
5404 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, in ci_dpm_enable()
5410 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_enable()
5412 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_enable()
5416 result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); in ci_dpm_enable()
5426 static void ci_dpm_disable(struct amdgpu_device *adev) in ci_dpm_disable() argument
5428 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_disable()
5429 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in ci_dpm_disable()
5431 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_disable()
5433 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in ci_dpm_disable()
5436 ci_dpm_powergate_uvd(adev, false); in ci_dpm_disable()
5438 if (!amdgpu_ci_is_smc_running(adev)) in ci_dpm_disable()
5441 ci_thermal_stop_thermal_controller(adev); in ci_dpm_disable()
5444 ci_enable_thermal_protection(adev, false); in ci_dpm_disable()
5445 ci_enable_power_containment(adev, false); in ci_dpm_disable()
5446 ci_enable_smc_cac(adev, false); in ci_dpm_disable()
5447 ci_enable_didt(adev, false); in ci_dpm_disable()
5448 ci_enable_spread_spectrum(adev, false); in ci_dpm_disable()
5449 ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false); in ci_dpm_disable()
5450 ci_stop_dpm(adev); in ci_dpm_disable()
5451 ci_enable_ds_master_switch(adev, false); in ci_dpm_disable()
5452 ci_enable_ulv(adev, false); in ci_dpm_disable()
5453 ci_clear_vc(adev); in ci_dpm_disable()
5454 ci_reset_to_default(adev); in ci_dpm_disable()
5455 ci_dpm_stop_smc(adev); in ci_dpm_disable()
5456 ci_force_switch_to_arb_f0(adev); in ci_dpm_disable()
5457 ci_enable_thermal_based_sclk_dpm(adev, false); in ci_dpm_disable()
5459 ci_update_current_ps(adev, boot_ps); in ci_dpm_disable()
5462 static int ci_dpm_set_power_state(struct amdgpu_device *adev) in ci_dpm_set_power_state() argument
5464 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_set_power_state()
5469 ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps); in ci_dpm_set_power_state()
5471 ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps); in ci_dpm_set_power_state()
5472 ret = ci_freeze_sclk_mclk_dpm(adev); in ci_dpm_set_power_state()
5477 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps); in ci_dpm_set_power_state()
5482 ret = ci_generate_dpm_level_enable_mask(adev, new_ps); in ci_dpm_set_power_state()
5488 ret = ci_update_vce_dpm(adev, new_ps, old_ps); in ci_dpm_set_power_state()
5494 ret = ci_update_sclk_t(adev); in ci_dpm_set_power_state()
5500 ret = ci_update_and_upload_mc_reg_table(adev); in ci_dpm_set_power_state()
5506 ret = ci_program_memory_timing_parameters(adev); in ci_dpm_set_power_state()
5511 ret = ci_unfreeze_sclk_mclk_dpm(adev); in ci_dpm_set_power_state()
5516 ret = ci_upload_dpm_level_enable_mask(adev); in ci_dpm_set_power_state()
5522 ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); in ci_dpm_set_power_state()
5528 static void ci_dpm_reset_asic(struct amdgpu_device *adev)
5530 ci_set_boot_state(adev);
5534 static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev) in ci_dpm_display_configuration_changed() argument
5536 ci_program_display_gap(adev); in ci_dpm_display_configuration_changed()
5562 static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev, in ci_parse_pplib_non_clock_info() argument
5580 adev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5582 adev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5585 static void ci_parse_pplib_clock_info(struct amdgpu_device *adev, in ci_parse_pplib_clock_info() argument
5589 struct ci_power_info *pi = ci_get_pi(adev); in ci_parse_pplib_clock_info()
5600 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, in ci_parse_pplib_clock_info()
5604 pl->pcie_lane = amdgpu_get_pcie_lane_support(adev, in ci_parse_pplib_clock_info()
5654 static int ci_parse_power_table(struct amdgpu_device *adev) in ci_parse_power_table() argument
5656 struct amdgpu_mode_info *mode_info = &adev->mode_info; in ci_parse_power_table()
5676 amdgpu_add_thermal_controller(adev); in ci_parse_power_table()
5688 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * in ci_parse_power_table()
5690 if (!adev->pm.dpm.ps) in ci_parse_power_table()
5701 kfree(adev->pm.dpm.ps); in ci_parse_power_table()
5704 adev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5705 ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in ci_parse_power_table()
5719 ci_parse_pplib_clock_info(adev, in ci_parse_power_table()
5720 &adev->pm.dpm.ps[i], k, in ci_parse_power_table()
5726 adev->pm.dpm.num_ps = state_array->ucNumEntries; in ci_parse_power_table()
5731 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5738 adev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5739 adev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5745 static int ci_get_vbios_boot_values(struct amdgpu_device *adev, in ci_get_vbios_boot_values() argument
5748 struct amdgpu_mode_info *mode_info = &adev->mode_info; in ci_get_vbios_boot_values()
5762 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev); in ci_get_vbios_boot_values()
5763 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev); in ci_get_vbios_boot_values()
5772 static void ci_dpm_fini(struct amdgpu_device *adev) in ci_dpm_fini() argument
5776 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5777 kfree(adev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5779 kfree(adev->pm.dpm.ps); in ci_dpm_fini()
5780 kfree(adev->pm.dpm.priv); in ci_dpm_fini()
5781 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5782 amdgpu_free_extended_power_table(adev); in ci_dpm_fini()
5794 static int ci_dpm_init_microcode(struct amdgpu_device *adev) in ci_dpm_init_microcode() argument
5802 switch (adev->asic_type) { in ci_dpm_init_microcode()
5815 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); in ci_dpm_init_microcode()
5818 err = amdgpu_ucode_validate(adev->pm.fw); in ci_dpm_init_microcode()
5825 release_firmware(adev->pm.fw); in ci_dpm_init_microcode()
5826 adev->pm.fw = NULL; in ci_dpm_init_microcode()
5831 static int ci_dpm_init(struct amdgpu_device *adev) in ci_dpm_init() argument
5845 adev->pm.dpm.priv = pi; in ci_dpm_init()
5847 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); in ci_dpm_init()
5864 ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state); in ci_dpm_init()
5866 ci_dpm_fini(adev); in ci_dpm_init()
5870 ret = amdgpu_get_platform_caps(adev); in ci_dpm_init()
5872 ci_dpm_fini(adev); in ci_dpm_init()
5876 ret = amdgpu_parse_extended_power_table(adev); in ci_dpm_init()
5878 ci_dpm_fini(adev); in ci_dpm_init()
5882 ret = ci_parse_power_table(adev); in ci_dpm_init()
5884 ci_dpm_fini(adev); in ci_dpm_init()
5914 ci_initialize_powertune_defaults(adev); in ci_dpm_init()
5923 ci_get_leakage_voltages(adev); in ci_dpm_init()
5924 ci_patch_dependency_tables_with_leakage(adev); in ci_dpm_init()
5925 ci_set_private_data_variables_based_on_pptable(adev); in ci_dpm_init()
5927 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5929 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5930 ci_dpm_fini(adev); in ci_dpm_init()
5933 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5934 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5935 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5936 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5937 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5938 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5939 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5940 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5941 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5943 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5944 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5945 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5947 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5948 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5949 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5950 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5952 if (adev->asic_type == CHIP_HAWAII) { in ci_dpm_init()
5966 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID); in ci_dpm_init()
5969 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5972 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5975 gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID); in ci_dpm_init()
5978 adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5981 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5984 gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID); in ci_dpm_init()
6016 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) in ci_dpm_init()
6018 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) in ci_dpm_init()
6021 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
6022 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) in ci_dpm_init()
6024 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) in ci_dpm_init()
6027 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
6030 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
6031 if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) in ci_dpm_init()
6033 else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) in ci_dpm_init()
6036 adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
6043 amdgpu_acpi_is_pcie_performance_request_supported(adev); in ci_dpm_init()
6048 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, in ci_dpm_init()
6059 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) in ci_dpm_init()
6069 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
6070 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
6071 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
6072 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()
6080 ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in ci_dpm_debugfs_print_current_performance_level() argument
6083 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_debugfs_print_current_performance_level()
6085 u32 sclk = ci_get_average_sclk_freq(adev); in ci_dpm_debugfs_print_current_performance_level()
6086 u32 mclk = ci_get_average_mclk_freq(adev); in ci_dpm_debugfs_print_current_performance_level()
6094 static void ci_dpm_print_power_state(struct amdgpu_device *adev, in ci_dpm_print_power_state() argument
6109 amdgpu_dpm_print_ps_status(adev, rps); in ci_dpm_print_power_state()
6112 static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low) in ci_dpm_get_sclk() argument
6114 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_sclk()
6123 static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low) in ci_dpm_get_mclk() argument
6125 struct ci_power_info *pi = ci_get_pi(adev); in ci_dpm_get_mclk()
6135 static int ci_dpm_get_temp(struct amdgpu_device *adev) in ci_dpm_get_temp() argument
6153 static int ci_set_temperature_range(struct amdgpu_device *adev) in ci_set_temperature_range() argument
6157 ret = ci_thermal_enable_alert(adev, false); in ci_set_temperature_range()
6160 ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, in ci_set_temperature_range()
6164 ret = ci_thermal_enable_alert(adev, true); in ci_set_temperature_range()
6172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_early_init() local
6174 ci_dpm_set_dpm_funcs(adev); in ci_dpm_early_init()
6175 ci_dpm_set_irq_funcs(adev); in ci_dpm_early_init()
6183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_late_init() local
6189 ret = amdgpu_pm_sysfs_init(adev); in ci_dpm_late_init()
6193 ret = ci_set_temperature_range(adev); in ci_dpm_late_init()
6197 ci_dpm_powergate_uvd(adev, true); in ci_dpm_late_init()
6205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_sw_init() local
6207 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); in ci_dpm_sw_init()
6211 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); in ci_dpm_sw_init()
6216 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in ci_dpm_sw_init()
6217 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in ci_dpm_sw_init()
6218 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; in ci_dpm_sw_init()
6219 adev->pm.default_sclk = adev->clock.default_sclk; in ci_dpm_sw_init()
6220 adev->pm.default_mclk = adev->clock.default_mclk; in ci_dpm_sw_init()
6221 adev->pm.current_sclk = adev->clock.default_sclk; in ci_dpm_sw_init()
6222 adev->pm.current_mclk = adev->clock.default_mclk; in ci_dpm_sw_init()
6223 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in ci_dpm_sw_init()
6228 ret = ci_dpm_init_microcode(adev); in ci_dpm_sw_init()
6232 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in ci_dpm_sw_init()
6233 mutex_lock(&adev->pm.mutex); in ci_dpm_sw_init()
6234 ret = ci_dpm_init(adev); in ci_dpm_sw_init()
6237 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in ci_dpm_sw_init()
6239 amdgpu_pm_print_power_states(adev); in ci_dpm_sw_init()
6240 mutex_unlock(&adev->pm.mutex); in ci_dpm_sw_init()
6246 ci_dpm_fini(adev); in ci_dpm_sw_init()
6247 mutex_unlock(&adev->pm.mutex); in ci_dpm_sw_init()
6254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_sw_fini() local
6256 mutex_lock(&adev->pm.mutex); in ci_dpm_sw_fini()
6257 amdgpu_pm_sysfs_fini(adev); in ci_dpm_sw_fini()
6258 ci_dpm_fini(adev); in ci_dpm_sw_fini()
6259 mutex_unlock(&adev->pm.mutex); in ci_dpm_sw_fini()
6268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_hw_init() local
6273 mutex_lock(&adev->pm.mutex); in ci_dpm_hw_init()
6274 ci_dpm_setup_asic(adev); in ci_dpm_hw_init()
6275 ret = ci_dpm_enable(adev); in ci_dpm_hw_init()
6277 adev->pm.dpm_enabled = false; in ci_dpm_hw_init()
6279 adev->pm.dpm_enabled = true; in ci_dpm_hw_init()
6280 mutex_unlock(&adev->pm.mutex); in ci_dpm_hw_init()
6287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_hw_fini() local
6289 if (adev->pm.dpm_enabled) { in ci_dpm_hw_fini()
6290 mutex_lock(&adev->pm.mutex); in ci_dpm_hw_fini()
6291 ci_dpm_disable(adev); in ci_dpm_hw_fini()
6292 mutex_unlock(&adev->pm.mutex); in ci_dpm_hw_fini()
6300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_suspend() local
6302 if (adev->pm.dpm_enabled) { in ci_dpm_suspend()
6303 mutex_lock(&adev->pm.mutex); in ci_dpm_suspend()
6305 ci_dpm_disable(adev); in ci_dpm_suspend()
6307 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in ci_dpm_suspend()
6308 mutex_unlock(&adev->pm.mutex); in ci_dpm_suspend()
6316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_resume() local
6318 if (adev->pm.dpm_enabled) { in ci_dpm_resume()
6320 mutex_lock(&adev->pm.mutex); in ci_dpm_resume()
6321 ci_dpm_setup_asic(adev); in ci_dpm_resume()
6322 ret = ci_dpm_enable(adev); in ci_dpm_resume()
6324 adev->pm.dpm_enabled = false; in ci_dpm_resume()
6326 adev->pm.dpm_enabled = true; in ci_dpm_resume()
6327 mutex_unlock(&adev->pm.mutex); in ci_dpm_resume()
6328 if (adev->pm.dpm_enabled) in ci_dpm_resume()
6329 amdgpu_pm_compute_clocks(adev); in ci_dpm_resume()
6348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in ci_dpm_print_status() local
6350 dev_info(adev->dev, "CIK DPM registers\n"); in ci_dpm_print_status()
6351 dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n", in ci_dpm_print_status()
6353 dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n", in ci_dpm_print_status()
6355 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n", in ci_dpm_print_status()
6357 dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n", in ci_dpm_print_status()
6359 dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n", in ci_dpm_print_status()
6361 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n", in ci_dpm_print_status()
6363 dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n", in ci_dpm_print_status()
6365 dev_info(adev->dev, " MC_ARB_CG=0x%08X\n", in ci_dpm_print_status()
6367 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", in ci_dpm_print_status()
6369 dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", in ci_dpm_print_status()
6371 dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", in ci_dpm_print_status()
6373 dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", in ci_dpm_print_status()
6375 dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n", in ci_dpm_print_status()
6377 dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n", in ci_dpm_print_status()
6379 dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", in ci_dpm_print_status()
6381 dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n", in ci_dpm_print_status()
6383 dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n", in ci_dpm_print_status()
6385 dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n", in ci_dpm_print_status()
6387 dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n", in ci_dpm_print_status()
6389 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", in ci_dpm_print_status()
6391 dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n", in ci_dpm_print_status()
6393 dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n", in ci_dpm_print_status()
6395 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n", in ci_dpm_print_status()
6397 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n", in ci_dpm_print_status()
6399 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n", in ci_dpm_print_status()
6401 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n", in ci_dpm_print_status()
6403 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n", in ci_dpm_print_status()
6405 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n", in ci_dpm_print_status()
6407 dev_info(adev->dev, " DLL_CNTL=0x%08X\n", in ci_dpm_print_status()
6409 dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n", in ci_dpm_print_status()
6411 dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n", in ci_dpm_print_status()
6413 dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n", in ci_dpm_print_status()
6415 dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n", in ci_dpm_print_status()
6417 dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n", in ci_dpm_print_status()
6419 dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n", in ci_dpm_print_status()
6421 dev_info(adev->dev, " MPLL_SS1=0x%08X\n", in ci_dpm_print_status()
6423 dev_info(adev->dev, " MPLL_SS2=0x%08X\n", in ci_dpm_print_status()
6425 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n", in ci_dpm_print_status()
6427 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n", in ci_dpm_print_status()
6429 dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n", in ci_dpm_print_status()
6431 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", in ci_dpm_print_status()
6433 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n", in ci_dpm_print_status()
6435 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n", in ci_dpm_print_status()
6437 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n", in ci_dpm_print_status()
6439 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n", in ci_dpm_print_status()
6441 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n", in ci_dpm_print_status()
6443 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n", in ci_dpm_print_status()
6445 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n", in ci_dpm_print_status()
6447 dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n", in ci_dpm_print_status()
6449 dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n", in ci_dpm_print_status()
6451 dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n", in ci_dpm_print_status()
6453 dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n", in ci_dpm_print_status()
6455 dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n", in ci_dpm_print_status()
6457 dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n", in ci_dpm_print_status()
6459 dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n", in ci_dpm_print_status()
6461 dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n", in ci_dpm_print_status()
6463 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n", in ci_dpm_print_status()
6465 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n", in ci_dpm_print_status()
6467 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n", in ci_dpm_print_status()
6469 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n", in ci_dpm_print_status()
6471 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n", in ci_dpm_print_status()
6473 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n", in ci_dpm_print_status()
6475 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n", in ci_dpm_print_status()
6477 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n", in ci_dpm_print_status()
6479 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n", in ci_dpm_print_status()
6481 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n", in ci_dpm_print_status()
6483 dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n", in ci_dpm_print_status()
6485 dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n", in ci_dpm_print_status()
6487 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n", in ci_dpm_print_status()
6489 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n", in ci_dpm_print_status()
6491 dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n", in ci_dpm_print_status()
6493 dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n", in ci_dpm_print_status()
6495 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n", in ci_dpm_print_status()
6497 dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n", in ci_dpm_print_status()
6499 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n", in ci_dpm_print_status()
6501 dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n", in ci_dpm_print_status()
6503 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n", in ci_dpm_print_status()
6505 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n", in ci_dpm_print_status()
6507 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n", in ci_dpm_print_status()
6509 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n", in ci_dpm_print_status()
6511 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n", in ci_dpm_print_status()
6513 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n", in ci_dpm_print_status()
6515 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n", in ci_dpm_print_status()
6517 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n", in ci_dpm_print_status()
6519 dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n", in ci_dpm_print_status()
6521 dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n", in ci_dpm_print_status()
6523 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n", in ci_dpm_print_status()
6525 dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n", in ci_dpm_print_status()
6527 dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n", in ci_dpm_print_status()
6529 dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n", in ci_dpm_print_status()
6531 dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n", in ci_dpm_print_status()
6533 dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n", in ci_dpm_print_status()
6535 dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", in ci_dpm_print_status()
6537 dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", in ci_dpm_print_status()
6539 dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", in ci_dpm_print_status()
6541 dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", in ci_dpm_print_status()
6543 dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", in ci_dpm_print_status()
6545 dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n", in ci_dpm_print_status()
6547 dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n", in ci_dpm_print_status()
6549 dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n", in ci_dpm_print_status()
6551 dev_info(adev->dev, " SMC_PC_C=0x%08X\n", in ci_dpm_print_status()
6560 static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev, in ci_dpm_set_interrupt_state() argument
6608 static int ci_dpm_process_interrupt(struct amdgpu_device *adev, in ci_dpm_process_interrupt() argument
6620 adev->pm.dpm.thermal.high_to_low = false; in ci_dpm_process_interrupt()
6625 adev->pm.dpm.thermal.high_to_low = true; in ci_dpm_process_interrupt()
6633 schedule_work(&adev->pm.dpm.thermal.work); in ci_dpm_process_interrupt()
6686 static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev) in ci_dpm_set_dpm_funcs() argument
6688 if (adev->pm.funcs == NULL) in ci_dpm_set_dpm_funcs()
6689 adev->pm.funcs = &ci_dpm_funcs; in ci_dpm_set_dpm_funcs()
6697 static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev) in ci_dpm_set_irq_funcs() argument
6699 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in ci_dpm_set_irq_funcs()
6700 adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs; in ci_dpm_set_irq_funcs()