221 		WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);  in ci_copy_and_switch_arb_sets()
222 		WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);  in ci_copy_and_switch_arb_sets()
227 		WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);  in ci_copy_and_switch_arb_sets()
228 		WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);  in ci_copy_and_switch_arb_sets()
237 	WREG32(mmMC_CG_CONFIG, mc_cg_config);  in ci_copy_and_switch_arb_sets()
721 				WREG32(config_regs->offset, data);  in ci_program_pt_config_registers()
1779 	WREG32(mmSMC_MSG_ARG_0, parameter);  in amdgpu_ci_send_msg_to_smc_with_parameter()
2027 	WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
2038 	WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4750 		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);  in ci_register_patching_mc_seq()
4753 		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);  in ci_register_patching_mc_seq()
4754 		WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);  in ci_register_patching_mc_seq()
4772 	WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));  in ci_initialize_mc_reg_table()
4773 	WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));  in ci_initialize_mc_reg_table()
4774 	WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));  in ci_initialize_mc_reg_table()
4775 	WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));  in ci_initialize_mc_reg_table()
4776 	WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));  in ci_initialize_mc_reg_table()
4777 	WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));  in ci_initialize_mc_reg_table()
4778 	WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));  in ci_initialize_mc_reg_table()
4779 	WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));  in ci_initialize_mc_reg_table()
4780 	WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));  in ci_initialize_mc_reg_table()
4781 	WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));  in ci_initialize_mc_reg_table()
4782 	WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));  in ci_initialize_mc_reg_table()
4783 	WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));  in ci_initialize_mc_reg_table()
4784 	WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));  in ci_initialize_mc_reg_table()
4785 	WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));  in ci_initialize_mc_reg_table()
4786 	WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));  in ci_initialize_mc_reg_table()
4787 	WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));  in ci_initialize_mc_reg_table()
4788 	WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));  in ci_initialize_mc_reg_table()
4789 	WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));  in ci_initialize_mc_reg_table()
4790 	WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));  in ci_initialize_mc_reg_table()
4791 	WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));  in ci_initialize_mc_reg_table()