Lines Matching defs:amdgpu_crtc

367 struct amdgpu_crtc {  struct
368 	struct drm_crtc base;
369 	int crtc_id;
370 	u16 lut_r[256], lut_g[256], lut_b[256];
371 	bool enabled;
372 	bool can_tile;
373 	uint32_t crtc_offset;
374 	struct drm_gem_object *cursor_bo;
375 	uint64_t cursor_addr;
376 	int cursor_x;
377 	int cursor_y;
378 	int cursor_hot_x;
379 	int cursor_hot_y;
380 	int cursor_width;
381 	int cursor_height;
382 	int max_cursor_width;
383 	int max_cursor_height;
384 	enum amdgpu_rmx_type rmx_type;
385 	u8 h_border;
386 	u8 v_border;
387 	fixed20_12 vsc;
388 	fixed20_12 hsc;
389 	struct drm_display_mode native_mode;
390 	u32 pll_id;
392 	struct workqueue_struct *pflip_queue;
393 	struct amdgpu_flip_work *pflip_works;
394 	enum amdgpu_flip_status pflip_status;
395 	int deferred_flip_completion;
397 	struct amdgpu_atom_ss ss;
398 	bool ss_enabled;
399 	u32 adjusted_clock;
400 	int bpc;
401 	u32 pll_reference_div;
402 	u32 pll_post_div;
403 	u32 pll_flags;
404 	struct drm_encoder *encoder;
405 	struct drm_connector *connector;
407 	u32 line_time;
408 	u32 wm_low;
409 	u32 wm_high;
410 	u32 lb_vblank_lead_lines;
411 	struct drm_display_mode hw_mode;