Lines Matching refs:uint64_t
258 uint64_t src_offset,
260 uint64_t dst_offset,
275 uint64_t dst_offset,
284 uint64_t pe, uint64_t src,
288 uint64_t pe,
289 uint64_t addr, unsigned count,
293 uint64_t pe,
294 uint64_t addr, unsigned count,
309 uint64_t addr, /* addr to write into pte/pde */
333 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
334 uint64_t seq, unsigned flags);
339 uint64_t pd_addr);
392 uint64_t gpu_addr;
395 uint64_t sync_seq[AMDGPU_MAX_RINGS];
416 uint64_t seq;
474 uint64_t src_offset,
475 uint64_t dst_offset,
493 uint64_t offset;
556 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
601 uint64_t gpu_addr;
637 uint32_t handle, uint64_t *offset_p);
645 uint64_t gpu_addr;
792 uint64_t base;
808 uint64_t gpu_addr;
821 uint64_t sequence;
860 uint64_t gpu_addr;
920 uint64_t addr;
925 uint64_t pd_gpu_addr;
993 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
1012 uint64_t addr, uint64_t offset,
1013 uint64_t size, uint32_t flags);
1016 uint64_t addr);
1028 uint64_t sequence;
1055 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1058 struct amdgpu_ring *ring, uint64_t seq);
1104 uint64_t save_restore_gpu_addr;
1110 uint64_t clear_state_gpu_addr;
1116 uint64_t cp_table_gpu_addr;
1294 uint64_t gpu_addr;
1675 uint64_t gpu_addr;
1697 uint64_t gpu_addr;
1841 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
2313 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2398 uint64_t addr, struct amdgpu_bo **bo);