153 					  struct zynq_gpio *gpio)  in zynq_gpio_get_bank_pin()  argument
157 	for (bank = 0; bank < gpio->p_data->max_bank; bank++) {  in zynq_gpio_get_bank_pin()
158 		if ((pin_num >= gpio->p_data->bank_min[bank]) &&  in zynq_gpio_get_bank_pin()
159 			(pin_num <= gpio->p_data->bank_max[bank])) {  in zynq_gpio_get_bank_pin()
162 						gpio->p_data->bank_min[bank];  in zynq_gpio_get_bank_pin()
186 	struct zynq_gpio *gpio = to_zynq_gpio(chip);  in zynq_gpio_get_value()  local
188 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_get_value()
190 	data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
210 	struct zynq_gpio *gpio = to_zynq_gpio(chip);  in zynq_gpio_set_value()  local
212 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_set_value()
230 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
247 	struct zynq_gpio *gpio = to_zynq_gpio(chip);  in zynq_gpio_dir_in()  local
249 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_dir_in()
256 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
258 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
280 	struct zynq_gpio *gpio = to_zynq_gpio(chip);  in zynq_gpio_dir_out()  local
282 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_dir_out()
285 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
287 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
290 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
292 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
310 	struct zynq_gpio *gpio =  in zynq_gpio_irq_mask()  local
314 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_mask()
316 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
331 	struct zynq_gpio *gpio =  in zynq_gpio_irq_unmask()  local
335 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_unmask()
337 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
351 	struct zynq_gpio *gpio =  in zynq_gpio_irq_ack()  local
355 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_ack()
357 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
402 	struct zynq_gpio *gpio =  in zynq_gpio_set_irq_type()  local
406 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_set_irq_type()
408 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
410 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
412 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
447 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
449 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
451 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
466 	struct zynq_gpio *gpio =  in zynq_gpio_set_wake()  local
469 	irq_set_irq_wake(gpio->irq, on);  in zynq_gpio_set_wake()
498 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,  in zynq_gpio_handle_bank_irq()  argument
502 	unsigned int bank_offset = gpio->p_data->bank_min[bank_num];  in zynq_gpio_handle_bank_irq()
503 	struct irq_domain *irqdomain = gpio->chip.irqdomain;  in zynq_gpio_handle_bank_irq()
532 	struct zynq_gpio *gpio =  in zynq_gpio_irqhandler()  local
538 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_irqhandler()
539 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
541 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
543 		zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);  in zynq_gpio_irqhandler()
576 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_runtime_suspend()  local
578 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_runtime_suspend()
586 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_runtime_resume()  local
588 	return clk_prepare_enable(gpio->clk);  in zynq_gpio_runtime_resume()
669 	struct zynq_gpio *gpio;  in zynq_gpio_probe()  local
674 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);  in zynq_gpio_probe()
675 	if (!gpio)  in zynq_gpio_probe()
683 	gpio->p_data = match->data;  in zynq_gpio_probe()
684 	platform_set_drvdata(pdev, gpio);  in zynq_gpio_probe()
687 	gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);  in zynq_gpio_probe()
688 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
689 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
691 	gpio->irq = platform_get_irq(pdev, 0);  in zynq_gpio_probe()
692 	if (gpio->irq < 0) {  in zynq_gpio_probe()
694 		return gpio->irq;  in zynq_gpio_probe()
698 	chip = &gpio->chip;  in zynq_gpio_probe()
699 	chip->label = gpio->p_data->label;  in zynq_gpio_probe()
709 	chip->ngpio = gpio->p_data->ngpio;  in zynq_gpio_probe()
712 	gpio->clk = devm_clk_get(&pdev->dev, NULL);  in zynq_gpio_probe()
713 	if (IS_ERR(gpio->clk)) {  in zynq_gpio_probe()
715 		return PTR_ERR(gpio->clk);  in zynq_gpio_probe()
717 	ret = clk_prepare_enable(gpio->clk);  in zynq_gpio_probe()
731 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)  in zynq_gpio_probe()
732 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()
742 	gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,  in zynq_gpio_probe()
753 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_probe()
766 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_remove()  local
769 	gpiochip_remove(&gpio->chip);  in zynq_gpio_remove()
770 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_remove()