109 	void __iomem *base_addr;  member
190 	data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
230 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
256 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
258 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
285 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
287 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
290 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
292 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
316 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
337 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
357 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
408 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
410 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
412 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
447 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
449 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
451 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
539 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
541 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
687 	gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);  in zynq_gpio_probe()
688 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
689 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
732 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()