Lines Matching refs:bank_num
151 unsigned int *bank_num, in zynq_gpio_get_bank_pin() argument
160 *bank_num = bank; in zynq_gpio_get_bank_pin()
169 *bank_num = 0; in zynq_gpio_get_bank_pin()
185 unsigned int bank_num, bank_pin_num; in zynq_gpio_get_value() local
188 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_get_value()
191 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); in zynq_gpio_get_value()
209 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
212 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_value()
217 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
219 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
246 unsigned int bank_num, bank_pin_num; in zynq_gpio_dir_in() local
249 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_in()
252 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) in zynq_gpio_dir_in()
256 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
258 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
279 unsigned int bank_num, bank_pin_num; in zynq_gpio_dir_out() local
282 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_out()
285 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
287 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
290 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
292 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
309 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_irq_mask() local
314 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_mask()
316 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_irq_mask()
330 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_irq_unmask() local
335 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_unmask()
337 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); in zynq_gpio_irq_unmask()
350 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_irq_ack() local
355 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_ack()
357 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irq_ack()
401 unsigned int device_pin_num, bank_num, bank_pin_num; in zynq_gpio_set_irq_type() local
406 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_irq_type()
409 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
411 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
413 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
447 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
449 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
451 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
499 unsigned int bank_num, in zynq_gpio_handle_bank_irq() argument
502 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; in zynq_gpio_handle_bank_irq()
531 unsigned int bank_num; in zynq_gpio_irqhandler() local
538 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_irqhandler()
540 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irqhandler()
542 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); in zynq_gpio_irqhandler()
543 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); in zynq_gpio_irqhandler()
668 int ret, bank_num; in zynq_gpio_probe() local
731 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) in zynq_gpio_probe()
733 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_probe()