244 	writel_relaxed(value, base + GPDR_OFFSET);  in pxa_gpio_direction_input()
257 	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));  in pxa_gpio_direction_output()
266 	writel_relaxed(tmp, base + GPDR_OFFSET);  in pxa_gpio_direction_output()
280 	writel_relaxed(1 << offset, gpio_chip_base(chip) +  in pxa_gpio_set()
354 	writel_relaxed(grer, c->regbase + GRER_OFFSET);  in update_edge_detect()
355 	writel_relaxed(gfer, c->regbase + GFER_OFFSET);  in update_edge_detect()
382 		writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);  in pxa_gpio_irq_type()
384 		writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);  in pxa_gpio_irq_type()
420 			writel_relaxed(gedr, c->regbase + GEDR_OFFSET);  in pxa_gpio_demux_handler()
438 	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);  in pxa_ack_muxed_gpio()
451 	writel_relaxed(grer, c->regbase + GRER_OFFSET);  in pxa_mask_muxed_gpio()
452 	writel_relaxed(gfer, c->regbase + GFER_OFFSET);  in pxa_mask_muxed_gpio()
633 		writel_relaxed(0, c->regbase + GFER_OFFSET);  in pxa_gpio_probe()
634 		writel_relaxed(0, c->regbase + GRER_OFFSET);  in pxa_gpio_probe()
635 		writel_relaxed(~0, c->regbase + GEDR_OFFSET);  in pxa_gpio_probe()
638 			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);  in pxa_gpio_probe()
712 		writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);  in pxa_gpio_suspend()
724 		writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);  in pxa_gpio_resume()
725 		writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);  in pxa_gpio_resume()
727 		writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);  in pxa_gpio_resume()
728 		writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);  in pxa_gpio_resume()
729 		writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);  in pxa_gpio_resume()