109 } ichx_priv;  variable
124 	spin_lock_irqsave(&ichx_priv.lock, flags);  in ichx_write_bit()
126 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_write_bit()
127 		data = ichx_priv.outlvl_cache[reg_nr];  in ichx_write_bit()
129 		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
130 				 ichx_priv.gpio_base);  in ichx_write_bit()
136 	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
137 			 ichx_priv.gpio_base);  in ichx_write_bit()
138 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_write_bit()
139 		ichx_priv.outlvl_cache[reg_nr] = data;  in ichx_write_bit()
141 	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_write_bit()
142 			ichx_priv.gpio_base);  in ichx_write_bit()
146 	spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ichx_write_bit()
158 	spin_lock_irqsave(&ichx_priv.lock, flags);  in ichx_read_bit()
160 	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],  in ichx_read_bit()
161 			 ichx_priv.gpio_base);  in ichx_read_bit()
163 	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)  in ichx_read_bit()
164 		data = ichx_priv.outlvl_cache[reg_nr] | data;  in ichx_read_bit()
166 	spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ichx_read_bit()
173 	return !!(ichx_priv.use_gpio & (1 << (nr / 32)));  in ichx_gpio_check_available()
197 	if (nr < 32 && ichx_priv.desc->have_blink)  in ichx_gpio_direction_output()
228 		if (!ichx_priv.pm_base)  in ich6_gpio_get()
231 		spin_lock_irqsave(&ichx_priv.lock, flags);  in ich6_gpio_get()
234 		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);  in ich6_gpio_get()
235 		data = ICHX_READ(0, ichx_priv.pm_base);  in ich6_gpio_get()
237 		spin_unlock_irqrestore(&ichx_priv.lock, flags);  in ich6_gpio_get()
256 	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))  in ichx_gpio_request()
285 	chip->dev = &ichx_priv.dev->dev;  in ichx_gpiolib_setup()
288 	chip->request = ichx_priv.desc->request ?  in ichx_gpiolib_setup()
289 		ichx_priv.desc->request : ichx_gpio_request;  in ichx_gpiolib_setup()
290 	chip->get = ichx_priv.desc->get ?  in ichx_gpiolib_setup()
291 		ichx_priv.desc->get : ichx_gpio_get;  in ichx_gpiolib_setup()
298 	chip->ngpio = ichx_priv.desc->ngpio;  in ichx_gpiolib_setup()
395 	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {  in ichx_gpio_request_regions()
399 				res_base->start + ichx_priv.desc->regs[0][i],  in ichx_gpio_request_regions()
400 				ichx_priv.desc->reglen[i], name))  in ichx_gpio_request_regions()
410 		release_region(res_base->start + ichx_priv.desc->regs[0][i],  in ichx_gpio_request_regions()
411 			       ichx_priv.desc->reglen[i]);  in ichx_gpio_request_regions()
420 	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {  in ichx_gpio_release_regions()
423 		release_region(res_base->start + ichx_priv.desc->regs[0][i],  in ichx_gpio_release_regions()
424 			       ichx_priv.desc->reglen[i]);  in ichx_gpio_release_regions()
437 	ichx_priv.dev = pdev;  in ichx_gpio_probe()
441 		ichx_priv.desc = &i3100_desc;  in ichx_gpio_probe()
444 		ichx_priv.desc = &intel5_desc;  in ichx_gpio_probe()
447 		ichx_priv.desc = &ich6_desc;  in ichx_gpio_probe()
450 		ichx_priv.desc = &ich7_desc;  in ichx_gpio_probe()
453 		ichx_priv.desc = &ich9_desc;  in ichx_gpio_probe()
456 		ichx_priv.desc = &ich10_corp_desc;  in ichx_gpio_probe()
459 		ichx_priv.desc = &ich10_cons_desc;  in ichx_gpio_probe()
462 		ichx_priv.desc = &avoton_desc;  in ichx_gpio_probe()
468 	spin_lock_init(&ichx_priv.lock);  in ichx_gpio_probe()
470 	ichx_priv.use_gpio = ich_info->use_gpio;  in ichx_gpio_probe()
472 					ichx_priv.use_gpio);  in ichx_gpio_probe()
476 	ichx_priv.gpio_base = res_base;  in ichx_gpio_probe()
483 	if (!ichx_priv.desc->uses_gpe0)  in ichx_gpio_probe()
498 	ichx_priv.pm_base = res_pm;  in ichx_gpio_probe()
501 	ichx_gpiolib_setup(&ichx_priv.chip);  in ichx_gpio_probe()
502 	err = gpiochip_add(&ichx_priv.chip);  in ichx_gpio_probe()
508 	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,  in ichx_gpio_probe()
509 	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);  in ichx_gpio_probe()
514 	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);  in ichx_gpio_probe()
515 	if (ichx_priv.pm_base)  in ichx_gpio_probe()
516 		release_region(ichx_priv.pm_base->start,  in ichx_gpio_probe()
517 				resource_size(ichx_priv.pm_base));  in ichx_gpio_probe()
523 	gpiochip_remove(&ichx_priv.chip);  in ichx_gpio_remove()
525 	ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);  in ichx_gpio_remove()
526 	if (ichx_priv.pm_base)  in ichx_gpio_remove()
527 		release_region(ichx_priv.pm_base->start,  in ichx_gpio_remove()
528 				resource_size(ichx_priv.pm_base));  in ichx_gpio_remove()