83 	struct regmap *regmap;  member
123 		regmap_update_bits(cg->regmap, mirqs0, mask, mask);  in crystalcove_update_irq_mask()
125 		regmap_update_bits(cg->regmap, mirqs0, mask, 0);  in crystalcove_update_irq_mask()
132 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);  in crystalcove_update_irq_ctrl()
142 	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),  in crystalcove_gpio_dir_in()
154 	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),  in crystalcove_gpio_dir_out()
167 	ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);  in crystalcove_gpio_get()
183 		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);  in crystalcove_gpio_set()
185 		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);  in crystalcove_gpio_set()
269 	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||  in crystalcove_gpio_irq_handler()
270 	    regmap_read(cg->regmap, GPIO1IRQ, &p1))  in crystalcove_gpio_irq_handler()
273 	regmap_write(cg->regmap, GPIO0IRQ, p0);  in crystalcove_gpio_irq_handler()
274 	regmap_write(cg->regmap, GPIO1IRQ, p1);  in crystalcove_gpio_irq_handler()
296 		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);  in crystalcove_gpio_dbg_show()
297 		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);  in crystalcove_gpio_dbg_show()
298 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,  in crystalcove_gpio_dbg_show()
300 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,  in crystalcove_gpio_dbg_show()
302 		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,  in crystalcove_gpio_dbg_show()
346 	cg->regmap = pmic->regmap;  in crystalcove_gpio_probe()