65 	void __iomem *reg_base;  member
86 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,  in bcm_kona_gpio_write_lock_regs()  argument
89 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);  in bcm_kona_gpio_write_lock_regs()
90 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_write_lock_regs()
102 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_lock_gpio()
104 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_lock_gpio()
118 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_unlock_gpio()
120 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_unlock_gpio()
128 	void __iomem *reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get_dir()  local
131 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;  in bcm_kona_gpio_get_dir()
138 	void __iomem *reg_base;  in bcm_kona_gpio_set()  local
145 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set()
154 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_set()
156 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_set()
165 	void __iomem *reg_base;  in bcm_kona_gpio_get()  local
172 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get()
181 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_get()
207 	void __iomem *reg_base;  in bcm_kona_gpio_direction_input()  local
212 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_input()
215 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
218 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
229 	void __iomem *reg_base;  in bcm_kona_gpio_direction_output()  local
236 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_output()
239 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
242 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
245 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
247 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
268 	void __iomem *reg_base;  in bcm_kona_gpio_set_debounce()  local
273 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set_debounce()
295 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
306 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
331 	void __iomem *reg_base;  in bcm_kona_gpio_irq_ack()  local
339 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_ack()
342 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
344 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
352 	void __iomem *reg_base;  in bcm_kona_gpio_irq_mask()  local
360 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_mask()
363 	val = readl(reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
365 	writel(val, reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
373 	void __iomem *reg_base;  in bcm_kona_gpio_irq_unmask()  local
381 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_unmask()
384 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
386 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
394 	void __iomem *reg_base;  in bcm_kona_gpio_irq_set_type()  local
401 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_set_type()
426 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
429 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
438 	void __iomem *reg_base;  in bcm_kona_gpio_irq_handler()  local
451 	reg_base = bank->kona_gpio->reg_base;  in bcm_kona_gpio_irq_handler()
454 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &  in bcm_kona_gpio_irq_handler()
455 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {  in bcm_kona_gpio_irq_handler()
465 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |  in bcm_kona_gpio_irq_handler()
466 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_handler()
547 	void __iomem *reg_base;  in bcm_kona_gpio_reset()  local
550 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_reset()
554 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);  in bcm_kona_gpio_reset()
555 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));  in bcm_kona_gpio_reset()
556 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));  in bcm_kona_gpio_reset()
558 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);  in bcm_kona_gpio_reset()
616 	kona_gpio->reg_base = devm_ioremap_resource(dev, res);  in bcm_kona_gpio_probe()
617 	if (IS_ERR(kona_gpio->reg_base)) {  in bcm_kona_gpio_probe()