131 static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,  in zynq_fpga_write()  argument
134 	writel(val, priv->io_base + offset);  in zynq_fpga_write()
137 static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,  in zynq_fpga_read()  argument
140 	return readl(priv->io_base + offset);  in zynq_fpga_read()
143 #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \  argument
144 	readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
147 static void zynq_fpga_mask_irqs(struct zynq_fpga_priv *priv)  in zynq_fpga_mask_irqs()  argument
151 	intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET);  in zynq_fpga_mask_irqs()
152 	zynq_fpga_write(priv, INT_MASK_OFFSET,  in zynq_fpga_mask_irqs()
156 static void zynq_fpga_unmask_irqs(struct zynq_fpga_priv *priv)  in zynq_fpga_unmask_irqs()  argument
160 	intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET);  in zynq_fpga_unmask_irqs()
161 	zynq_fpga_write(priv, INT_MASK_OFFSET,  in zynq_fpga_unmask_irqs()
168 	struct zynq_fpga_priv *priv = data;  in zynq_fpga_isr()  local
171 	zynq_fpga_mask_irqs(priv);  in zynq_fpga_isr()
173 	complete(&priv->dma_done);  in zynq_fpga_isr()
181 	struct zynq_fpga_priv *priv;  in zynq_fpga_ops_write_init()  local
185 	priv = mgr->priv;  in zynq_fpga_ops_write_init()
187 	err = clk_enable(priv->clk);  in zynq_fpga_ops_write_init()
194 		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,  in zynq_fpga_ops_write_init()
198 		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,  in zynq_fpga_ops_write_init()
201 		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,  in zynq_fpga_ops_write_init()
210 		ctrl = zynq_fpga_read(priv, CTRL_OFFSET);  in zynq_fpga_ops_write_init()
213 		zynq_fpga_write(priv, CTRL_OFFSET, ctrl);  in zynq_fpga_ops_write_init()
215 		err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,  in zynq_fpga_ops_write_init()
220 			dev_err(priv->dev, "Timeout waiting for PCFG_INIT");  in zynq_fpga_ops_write_init()
224 		ctrl = zynq_fpga_read(priv, CTRL_OFFSET);  in zynq_fpga_ops_write_init()
227 		zynq_fpga_write(priv, CTRL_OFFSET, ctrl);  in zynq_fpga_ops_write_init()
229 		err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,  in zynq_fpga_ops_write_init()
234 			dev_err(priv->dev, "Timeout waiting for !PCFG_INIT");  in zynq_fpga_ops_write_init()
238 		ctrl = zynq_fpga_read(priv, CTRL_OFFSET);  in zynq_fpga_ops_write_init()
241 		zynq_fpga_write(priv, CTRL_OFFSET, ctrl);  in zynq_fpga_ops_write_init()
243 		err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,  in zynq_fpga_ops_write_init()
248 			dev_err(priv->dev, "Timeout waiting for PCFG_INIT");  in zynq_fpga_ops_write_init()
258 	ctrl = zynq_fpga_read(priv, CTRL_OFFSET);  in zynq_fpga_ops_write_init()
259 	zynq_fpga_write(priv, CTRL_OFFSET,  in zynq_fpga_ops_write_init()
263 	status = zynq_fpga_read(priv, STATUS_OFFSET);  in zynq_fpga_ops_write_init()
265 		dev_err(priv->dev, "DMA command queue full");  in zynq_fpga_ops_write_init()
271 	ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);  in zynq_fpga_ops_write_init()
272 	zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));  in zynq_fpga_ops_write_init()
274 	clk_disable(priv->clk);  in zynq_fpga_ops_write_init()
279 	clk_disable(priv->clk);  in zynq_fpga_ops_write_init()
287 	struct zynq_fpga_priv *priv;  in zynq_fpga_ops_write()  local
296 	priv = mgr->priv;  in zynq_fpga_ops_write()
298 	kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr, GFP_KERNEL);  in zynq_fpga_ops_write()
305 	err = clk_enable(priv->clk);  in zynq_fpga_ops_write()
309 	zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);  in zynq_fpga_ops_write()
311 	reinit_completion(&priv->dma_done);  in zynq_fpga_ops_write()
314 	zynq_fpga_unmask_irqs(priv);  in zynq_fpga_ops_write()
319 	zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, (u32)(dma_addr) + 1);  in zynq_fpga_ops_write()
320 	zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, (u32)DMA_INVALID_ADDRESS);  in zynq_fpga_ops_write()
325 	zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, transfer_length);  in zynq_fpga_ops_write()
326 	zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);  in zynq_fpga_ops_write()
328 	wait_for_completion(&priv->dma_done);  in zynq_fpga_ops_write()
330 	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);  in zynq_fpga_ops_write()
331 	zynq_fpga_write(priv, INT_STS_OFFSET, intr_status);  in zynq_fpga_ops_write()
334 		dev_err(priv->dev, "Error configuring FPGA");  in zynq_fpga_ops_write()
338 	clk_disable(priv->clk);  in zynq_fpga_ops_write()
341 	dma_free_coherent(priv->dev, in_count, kbuf, dma_addr);  in zynq_fpga_ops_write()
348 	struct zynq_fpga_priv *priv = mgr->priv;  in zynq_fpga_ops_write_complete()  local
352 	err = clk_enable(priv->clk);  in zynq_fpga_ops_write_complete()
356 	err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,  in zynq_fpga_ops_write_complete()
361 	clk_disable(priv->clk);  in zynq_fpga_ops_write_complete()
369 		regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,  in zynq_fpga_ops_write_complete()
373 		regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,  in zynq_fpga_ops_write_complete()
384 	struct zynq_fpga_priv *priv;  in zynq_fpga_ops_state()  local
386 	priv = mgr->priv;  in zynq_fpga_ops_state()
388 	err = clk_enable(priv->clk);  in zynq_fpga_ops_state()
392 	intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);  in zynq_fpga_ops_state()
393 	clk_disable(priv->clk);  in zynq_fpga_ops_state()
411 	struct zynq_fpga_priv *priv;  in zynq_fpga_probe()  local
415 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);  in zynq_fpga_probe()
416 	if (!priv)  in zynq_fpga_probe()
419 	priv->dev = dev;  in zynq_fpga_probe()
422 	priv->io_base = devm_ioremap_resource(dev, res);  in zynq_fpga_probe()
423 	if (IS_ERR(priv->io_base))  in zynq_fpga_probe()
424 		return PTR_ERR(priv->io_base);  in zynq_fpga_probe()
426 	priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,  in zynq_fpga_probe()
428 	if (IS_ERR(priv->slcr)) {  in zynq_fpga_probe()
430 		return PTR_ERR(priv->slcr);  in zynq_fpga_probe()
433 	init_completion(&priv->dma_done);  in zynq_fpga_probe()
435 	priv->irq = platform_get_irq(pdev, 0);  in zynq_fpga_probe()
436 	if (priv->irq < 0) {  in zynq_fpga_probe()
438 		return priv->irq;  in zynq_fpga_probe()
441 	err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0,  in zynq_fpga_probe()
442 			       dev_name(dev), priv);  in zynq_fpga_probe()
448 	priv->clk = devm_clk_get(dev, "ref_clk");  in zynq_fpga_probe()
449 	if (IS_ERR(priv->clk)) {  in zynq_fpga_probe()
451 		return PTR_ERR(priv->clk);  in zynq_fpga_probe()
454 	err = clk_prepare_enable(priv->clk);  in zynq_fpga_probe()
461 	zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);  in zynq_fpga_probe()
463 	clk_disable(priv->clk);  in zynq_fpga_probe()
466 				&zynq_fpga_ops, priv);  in zynq_fpga_probe()
469 		clk_unprepare(priv->clk);  in zynq_fpga_probe()
478 	struct zynq_fpga_priv *priv;  in zynq_fpga_remove()  local
482 	priv = mgr->priv;  in zynq_fpga_remove()
486 	clk_unprepare(priv->clk);  in zynq_fpga_remove()