58 static void tile_edac_check(struct mem_ctl_info *mci)  in tile_edac_check()  argument
60 	struct tile_edac_priv	*priv = mci->pvt_info;  in tile_edac_check()
72 		dev_dbg(mci->pdev, "ECC CE err on node %d\n", priv->node);  in tile_edac_check()
74 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,  in tile_edac_check()
77 				     mci->ctl_name, "");  in tile_edac_check()
85 static int tile_edac_init_csrows(struct mem_ctl_info *mci)  in tile_edac_init_csrows()  argument
87 	struct csrow_info	*csrow = mci->csrows[0];  in tile_edac_init_csrows()
88 	struct tile_edac_priv	*priv = mci->pvt_info;  in tile_edac_init_csrows()
127 	struct mem_ctl_info	*mci;  in tile_edac_mc_probe()  local
144 	mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,  in tile_edac_mc_probe()
146 	if (mci == NULL)  in tile_edac_mc_probe()
148 	priv = mci->pvt_info;  in tile_edac_mc_probe()
152 	mci->pdev = &pdev->dev;  in tile_edac_mc_probe()
153 	mci->mtype_cap = MEM_FLAG_DDR2;  in tile_edac_mc_probe()
154 	mci->edac_ctl_cap = EDAC_FLAG_SECDED;  in tile_edac_mc_probe()
156 	mci->mod_name = DRV_NAME;  in tile_edac_mc_probe()
158 	mci->ctl_name = "TILEGx_Memory_Controller";  in tile_edac_mc_probe()
160 	mci->ctl_name = "TILEPro_Memory_Controller";  in tile_edac_mc_probe()
162 	mci->dev_name = dev_name(&pdev->dev);  in tile_edac_mc_probe()
163 	mci->edac_check = tile_edac_check;  in tile_edac_mc_probe()
169 	if (tile_edac_init_csrows(mci)) {  in tile_edac_mc_probe()
171 		mci->edac_cap = EDAC_FLAG_NONE;  in tile_edac_mc_probe()
173 		mci->edac_cap = EDAC_FLAG_SECDED;  in tile_edac_mc_probe()
176 	platform_set_drvdata(pdev, mci);  in tile_edac_mc_probe()
179 	rc = edac_mc_add_mc(mci);  in tile_edac_mc_probe()
182 		edac_mc_free(mci);  in tile_edac_mc_probe()
191 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);  in tile_edac_mc_remove()  local
194 	if (mci)  in tile_edac_mc_remove()
195 		edac_mc_free(mci);  in tile_edac_mc_remove()